Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753544AbdDCPSs (ORCPT ); Mon, 3 Apr 2017 11:18:48 -0400 Received: from mail.kapsi.fi ([217.30.184.167]:59474 "EHLO mail.kapsi.fi" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751716AbdDCPSq (ORCPT ); Mon, 3 Apr 2017 11:18:46 -0400 Subject: Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster To: Thierry Reding , Mikko Perttunen References: <1491223345-24386-1-git-send-email-mperttunen@nvidia.com> <1491223345-24386-2-git-send-email-mperttunen@nvidia.com> <20170403140617.GA22966@ulmo.ba.sec> Cc: rjw@rjwysocki.net, viresh.kumar@linaro.org, jonathanh@nvidia.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org From: Mikko Perttunen Message-ID: Date: Mon, 3 Apr 2017 18:18:43 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <20170403140617.GA22966@ulmo.ba.sec> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 84.249.193.183 X-SA-Exim-Mail-From: cyndis@kapsi.fi X-SA-Exim-Scanned: No (on mail.kapsi.fi); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1969 Lines: 55 On 04/03/2017 05:06 PM, Thierry Reding wrote: > On Mon, Apr 03, 2017 at 03:42:24PM +0300, Mikko Perttunen wrote: >> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped >> registers that initiate CPU frequency/voltage transitions. >> >> Signed-off-by: Mikko Perttunen >> --- >> .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> >> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> new file mode 100644 >> index 000000000000..50cd615219e9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> @@ -0,0 +1,22 @@ >> +NVIDIA Tegra CCPLEX_CLUSTER area >> + >> +Required properties: >> +- compatible: Should contain one of the following: >> + - "nvidia,tegra186-ccplex-cluster": for Tegra186 >> +- reg: Must contain an (offset, length) pair of the register set for each >> + entry in reg-names. >> +- reg-names: Must include the following entries: >> + - "a57": Public aperture for A57 CPU cluster >> + - "denver": Public aperture for Denver CPU cluster >> +- nvidia,bpmp: Phandle to BPMP device that can be queried for OPP tables > > "phandle" Will fix. > >> +Example: >> + >> + ccplex@e000000 { >> + compatible = "nvidia,tegra186-ccplex-cluster"; >> + reg = <0x0 0x0e060000 0x0 0x1000>, >> + <0x0 0x0e070000 0x0 0x1000>; >> + reg-names = "a57", "denver"; >> + >> + nvidia,bpmp = <&bpmp>; >> + }; > > Where's the information about the register offsets coming from? The TRM > says that CCPLEX_CLUSTER has a single aperture from 0x0e000000 to > 0x0e3fffff. Some internal document with a name related to Denver power management, IIRC. I'll link it to you tomorrow. > > Thierry >