Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752927AbdDCRs4 (ORCPT ); Mon, 3 Apr 2017 13:48:56 -0400 Received: from foss.arm.com ([217.140.101.70]:34310 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751883AbdDCRsz (ORCPT ); Mon, 3 Apr 2017 13:48:55 -0400 Date: Mon, 3 Apr 2017 18:49:11 +0100 From: Will Deacon To: Sunil Kovvuri Cc: Robin Murphy , iommu@lists.linux-foundation.org, LAKML , LKML , Sunil Goutham Subject: Re: [PATCH] iommu/arm-smmu: Fix 16bit ASID configuration Message-ID: <20170403174911.GJ5706@arm.com> References: <1490697672-15928-1-git-send-email-sunil.kovvuri@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3450 Lines: 82 On Mon, Apr 03, 2017 at 11:16:33PM +0530, Sunil Kovvuri wrote: > On Tue, Mar 28, 2017 at 4:11 PM, wrote: > > From: Sunil Goutham > > > > 16bit ASID should be enabled before initializing TTBR0/1, > > otherwise only LSB 8bit ASID will be considered. Hence > > moving configuration of TTBCR register ahead of TTBR0/1 > > while initializing context bank. > > > > Signed-off-by: Sunil Goutham > > --- > > drivers/iommu/arm-smmu.c | 41 ++++++++++++++++++++++------------------- > > 1 file changed, 22 insertions(+), 19 deletions(-) > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > index 9b33700..2845d73 100644 > > --- a/drivers/iommu/arm-smmu.c > > +++ b/drivers/iommu/arm-smmu.c > > @@ -758,6 +758,28 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, > > } > > writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); > > > > + /* TTBCR */ > > + if (stage1) { > > + if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { > > + reg = pgtbl_cfg->arm_v7s_cfg.tcr; > > + reg2 = 0; > > + } else { > > + reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; > > + reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; > > + reg2 |= TTBCR2_SEP_UPSTREAM; > > + /* 16bit ASID should be enabled before write to TTBR, > > + * otherwise only LSB 8bit will be considered. > > + */ > > + if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) > > + reg2 |= TTBCR2_AS; > > + } > > + if (smmu->version > ARM_SMMU_V1) > > + writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2); > > + } else { > > + reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; > > + } > > + writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); > > + > > /* TTBRs */ > > if (stage1) { > > u16 asid = ARM_SMMU_CB_ASID(smmu, cfg); > > @@ -781,25 +803,6 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, > > writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0); > > } > > > > - /* TTBCR */ > > - if (stage1) { > > - if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { > > - reg = pgtbl_cfg->arm_v7s_cfg.tcr; > > - reg2 = 0; > > - } else { > > - reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; > > - reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; > > - reg2 |= TTBCR2_SEP_UPSTREAM; > > - if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) > > - reg2 |= TTBCR2_AS; > > - } > > - if (smmu->version > ARM_SMMU_V1) > > - writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2); > > - } else { > > - reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; > > - } > > - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); > > - > > /* MAIRs (stage-1 only) */ > > if (stage1) { > > if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { > > -- > > 2.7.4 > > > > Any comments or feedback on this patch ? I've picked it up. Will