Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752742AbdDDH3m (ORCPT ); Tue, 4 Apr 2017 03:29:42 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:35073 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751094AbdDDH3k (ORCPT ); Tue, 4 Apr 2017 03:29:40 -0400 Subject: Re: [PATCH v2 1/2] dt-bindings: Document the STM32 QSPI bindings To: Rob Herring References: <1490979724-10905-1-git-send-email-ludovic.Barre@st.com> <1490979724-10905-2-git-send-email-ludovic.Barre@st.com> <20170403165735.sopfhlxzefkzrbfh@rob-hp-laptop> CC: Cyrille Pitchen , Marek Vasut , David Woodhouse , Brian Norris , Boris Brezillon , Richard Weinberger , Alexandre Torgue , , , From: Ludovic BARRE Message-ID: Date: Tue, 4 Apr 2017 09:28:33 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20170403165735.sopfhlxzefkzrbfh@rob-hp-laptop> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG3NODE3.st.com (10.75.127.9) To SFHDAG6NODE1.st.com (10.75.127.16) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-04-04_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3199 Lines: 92 Hi Rob thanks for review my comments below br Ludo On 04/03/2017 06:57 PM, Rob Herring wrote: > On Fri, Mar 31, 2017 at 07:02:03PM +0200, Ludovic Barre wrote: >> From: Ludovic Barre >> >> This patch adds documentation of device tree bindings for the STM32 >> QSPI controller. >> >> Signed-off-by: Ludovic Barre >> --- >> .../devicetree/bindings/mtd/stm32-quadspi.txt | 45 ++++++++++++++++++++++ >> 1 file changed, 45 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >> >> diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >> new file mode 100644 >> index 0000000..95a8ebd >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >> @@ -0,0 +1,45 @@ >> +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) >> + >> +Required properties: >> +- compatible: should be "st,stm32f469-qspi" >> +- reg: contains the register location and length. >> + (optional) the memory mapping address and length > Why optional? Either the h/w has it or doesn't. If some chips don't, > they should have a different compatible string. in fact, the stm32 qspi controller can operate in any of the following modes: -indirect mode: all the operations are performed using the qspi registers with read/write. -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory (use memcpy_fromio). this mode improve read throughput if qspi_mm is defined the qspi controller use read memory-mapped mode else the controller transfers in indirect mode. >> +- reg-names: list of the names corresponding to the previous register >> + Should contain "qspi" to register location >> + (optional) "qspi_mm" if read in memory map mode (improve read throughput) >> +- interrupts: should contain the interrupt for the device >> +- clocks: the phandle of the clock needed by the QSPI controller >> +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer >> + >> +Optional properties: >> +- resets: must contain the phandle to the reset controller. >> + >> +A spi flash must be a child of the nor_flash node and could have some >> +properties. Also see jedec,spi-nor.txt. >> + >> +Required properties: >> +- reg: chip-Select number (QSPI controller may connect 2 nor flashes) >> +- spi-max-frequency: max frequency of spi bus >> + >> +Optional property: >> +- spi-rx-bus-width: the bus width (number of data wires) > Just "see ../spi/spi-bus.txt" for the description ok > >> + >> +Example: >> + >> +qspi: qspi@a0001000 { > spi@... ok >> + compatible = "st,stm32f469-qspi"; >> + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; >> + reg-names = "qspi", "qspi_mm"; >> + interrupts = <91>; >> + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; >> + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_qspi0>; >> + >> + flash@0 { >> + reg = <0>; >> + spi-rx-bus-width = <4>; >> + spi-max-frequency = <108000000>; >> + ... >> + }; >> +}; >> -- >> 2.7.4 >>