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Date: Tue, 4 Apr 2017 09:55:07 +0100
From: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
To: Daniel Baluta <daniel.baluta@gmail.com>
CC: Mark Brown <broonie@kernel.org>, Liam Girdwood <lgirdwood@gmail.com>,
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Subject: Re: [alsa-devel][PATCH v2 2/2] ASoC: wm8960: Let wm8960 driver
 configure its bit clock and frame clock
Message-ID: <20170404085507.GW6986@localhost.localdomain>
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On Tue, Apr 04, 2017 at 10:55:00AM +0300, Daniel Baluta wrote:
> <Removing Zidan from thread because the address no longer exists>
> 
> On Mon, Apr 3, 2017 at 4:54 PM, Charles Keepax
> <ckeepax@opensource.wolfsonmicro.com> wrote:
> > On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
> >> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
> >> <ckeepax@opensource.wolfsonmicro.com> wrote:
> > Is the problem here that the PLL part of the code is making the
> > same assumption as the direct part of the code was, that the bclk
> > should be exact?
> 
> Yes.
> 
> 
> After wm8960_configure_sysclk fails to find a LRCLK, we try to use the
> PLL.
> 
> Anyhow, here we don't even reach to check if the PLL can be used because
> there is no solution for the following system:
> 
> freq_out = sysclk * sysclk_divs[i];
> sysclk = lrclk * dac_divs[j];
> sysclk == bclk * bclk_divs[k]
> 
> 
> Perhaps, we can also try here to relax bitclk computation like we did for when
> sysclk was directly derived from mclk.

Exactly that is what I am saying it looks like the PLL part
of the process still assumes it requires bclk to be an exact
frequency if we relax that, the same way we did for the direct
MCLK then we should be good.

Thanks,
Charles