Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754932AbdDDTOo (ORCPT ); Tue, 4 Apr 2017 15:14:44 -0400 Received: from mga04.intel.com ([192.55.52.120]:50225 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754180AbdDDTOm (ORCPT ); Tue, 4 Apr 2017 15:14:42 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,275,1486454400"; d="scan'208";a="1130932100" From: kan.liang@intel.com To: mingo@redhat.com, peterz@infradead.org, linux-kernel@vger.kernel.org Cc: eranian@google.com, ak@linux.intel.com, Kan Liang Subject: [PATCH V2] perf/x86: fix spurious NMI with PEBS Load Latency event Date: Tue, 4 Apr 2017 15:14:06 -0400 Message-Id: <1491333246-3965-1-git-send-email-kan.liang@intel.com> X-Mailer: git-send-email 2.4.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2929 Lines: 81 From: Kan Liang Spurious NMIs will be observed when applying the following command. while true ; do sudo perf record -b -a -e "cpu/umask=0x01,event=0xcd,ldlat=0x80/pp,cpu/umask=0x03,event=0x0/, cpu/umask=0x02,event=0x0/,cycles,branches,cache-misses, cache-references" -- sleep 10 ; done The issue was introduced by commit 8077eca079a2 ("perf/x86/pebs: Add workaround for broken OVFL status on HSW+") The previous patch clear the status's bits for the counters used for PEBS events, by masking the whole 64 bits pebs_enabled. However, only the lower 32 bits of both status and pebs_enabled are reserved for PEBS-able counters. For status, the first three bits of upper 32 bits are fixed counter overflow bit. For pebs_enabled, the first three bits of upper 32 bits are for PEBS Load Latency event. In the test case, the PEBS Load Latency event and fixed counter event could be overflowed at the same time. The fixed counter overflow bit will be cleared by mistake. Once it is cleared, the fixed counter overflow never be processed, which finally trigger spurious NMI. Correct the PEBS enabled mask by ignoring the non-PEBS bits. Fixes: 8077eca079a2 ("perf/x86/pebs: Add workaround for broken OVFL status on HSW+") Signed-off-by: Kan Liang --- Change since V1: - using a macros for (1ULL << MAX_PEBS_EVENTS) - 1) arch/x86/events/intel/core.c | 2 +- arch/x86/events/intel/ds.c | 2 +- arch/x86/events/perf_event.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 319da60..3411e79 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2151,7 +2151,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) * counters from the GLOBAL_STATUS mask and we always process PEBS * events via drain_pebs(). */ - status &= ~cpuc->pebs_enabled; + status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); /* * PEBS overflow sets bit 62 in the global status register diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 9dfeeec..c6d23ff 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1222,7 +1222,7 @@ get_next_pebs_record_by_bit(void *base, void *top, int bit) /* clear non-PEBS bit and re-check */ pebs_status = p->status & cpuc->pebs_enabled; - pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1; + pebs_status &= PEBS_COUNTER_MASK; if (pebs_status == (1 << bit)) return at; } diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 416f565..2469fba 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -79,6 +79,7 @@ struct amd_nb { /* The maximal number of PEBS events: */ #define MAX_PEBS_EVENTS 8 +#define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) /* * Flags PEBS can handle without an PMI. -- 2.4.3