Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754810AbdDDWKK (ORCPT ); Tue, 4 Apr 2017 18:10:10 -0400 Received: from mail.kernel.org ([198.145.29.136]:41538 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752997AbdDDWKH (ORCPT ); Tue, 4 Apr 2017 18:10:07 -0400 MIME-Version: 1.0 In-Reply-To: <1490875696-15145-5-git-send-email-hao.wu@intel.com> References: <1490875696-15145-1-git-send-email-hao.wu@intel.com> <1490875696-15145-5-git-send-email-hao.wu@intel.com> From: Alan Tull Date: Tue, 4 Apr 2017 17:09:23 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 04/16] fpga: intel: pcie: parse feature list and create platform device for features. To: Wu Hao Cc: Moritz Fischer , linux-fpga@vger.kernel.org, linux-kernel , luwei.kang@intel.com, yi.z.zhang@intel.com, Xiao Guangrong , Tim Whisonant , Enno Luebbers , Shiva Rao , Christopher Rauer Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1754 Lines: 36 On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao wrote: > From: Xiao Guangrong > > Device Featuer List structure creates a link list of feature headers > within the MMIO space to provide an extensiable way of adding features. > > The Intel FPGA PCIe driver walks through the feature headers to enumerate > feature devices, FPGA Management Engine (FME) and FPGA Port for Accelerated > Function Unit (AFU), and their private sub features. For feature devices, > it creates the platform devices and linked the private sub features into > their platform data. > I'm still looking at this code and it's pretty new to me, but I think it would be desirable and not really hard to separate the code that enumerates from all the fixed feature code. So pcie.c could see that there is a pci device out there that it knows has these memory mapped enumeration structs. So it goes and reads the structs, parses them, and knows what drivers to probe. The FME and AFU and other fpga device drivers could register their guids with the framework and be discoverable in that way. That way if you need to implement a different FME or anything else, it could be added with a new guid to this framework and would get enumerated. I'm thinking of the future and of more general usability of this code. Then the enumeration code wouldn't have to be 'intel' code or even code dedicated to FME's and AFU's. Any FPGA with a PCIe port that has the right id's could have this struct and use this enumeration method. Actually if the parse* enumeration code could be in a separate file as helper functions for the pcie code, this stuff would be structured for future support this of the same framework on embedded FPGA devices. Alan