Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755000AbdDEJWO (ORCPT ); Wed, 5 Apr 2017 05:22:14 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:54529 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933070AbdDEJUm (ORCPT ); Wed, 5 Apr 2017 05:20:42 -0400 From: Juergen Borleis To: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, f.fainelli@gmail.com, kernel@pengutronix.de, andrew@lunn.ch, vivien.didelot@savoirfairelinux.com, davem@davemloft.net Subject: [PATCH 2/4] net: dsa: add new DSA switch driver for the SMSC-LAN9303 Date: Wed, 5 Apr 2017 11:20:22 +0200 Message-Id: <20170405092024.16048-3-jbe@pengutronix.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170405092024.16048-1-jbe@pengutronix.de> References: <20170405092024.16048-1-jbe@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: jbe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 29875 Lines: 973 The SMSC/Microchip LAN9303 is an ethernet switch device with one CPU port and two external ethernet ports with built-in phys. This driver uses the DSA framework, but is currently only capable of separating the two external ports. There is no offload support yet. Signed-off-by: Juergen Borleis --- drivers/net/phy/lan9303-core.c | 924 +++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/lan9303.h | 21 + 2 files changed, 945 insertions(+) create mode 100644 drivers/net/phy/lan9303-core.c create mode 100644 drivers/net/phy/lan9303.h diff --git a/drivers/net/phy/lan9303-core.c b/drivers/net/phy/lan9303-core.c new file mode 100644 index 0000000000000..1c4698f0e13dc --- /dev/null +++ b/drivers/net/phy/lan9303-core.c @@ -0,0 +1,924 @@ +/* + * Copyright (C) 2017 Pengutronix, Juergen Borleis + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include + +#include "lan9303.h" + +#define LAN9303_CHIP_REV 0x14 +#define LAN9303_IRQ_CFG 0x15 +# define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) +# define LAN9303_IRQ_CFG_IRQ_POL BIT(4) +# define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) +#define LAN9303_INT_STS 0x16 +# define LAN9303_INT_STS_PHY_INT2 BIT(27) +# define LAN9303_INT_STS_PHY_INT1 BIT(26) +#define LAN9303_INT_EN 0x17 +# define LAN9303_INT_EN_PHY_INT2_EN BIT(27) +# define LAN9303_INT_EN_PHY_INT1_EN BIT(26) +#define LAN9303_HW_CFG 0x1D +# define LAN9303_HW_CFG_READY BIT(27) +# define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) +# define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) +#define LAN9303_PMI_DATA 0x29 +#define LAN9303_PMI_ACCESS 0x2A +# define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) +# define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) +#define LAN9303_MANUAL_FC_1 0x68 +#define LAN9303_MANUAL_FC_2 0x69 +#define LAN9303_MANUAL_FC_0 0x6a +#define LAN9303_SWITCH_CSR_DATA 0x6b +#define LAN9303_SWITCH_CSR_CMD 0x6c +#define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) +#define LAN9303_SWITCH_CSR_CMD_RW BIT(30) +#define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) +#define LAN9303_VIRT_PHY_BASE 0x70 +#define LAN9303_VIRT_SPECIAL_CTRL 0x77 + +#define LAN9303_SW_DEV_ID 0x0000 +#define LAN9303_SW_RESET 0x0001 +#define LAN9303_SW_RESET_RESET BIT(0) +#define LAN9303_SW_IMR 0x0004 +#define LAN9303_SW_IPR 0x0005 +#define LAN9303_MAC_VER_ID_0 0x0400 +#define LAN9303_MAC_RX_CFG_0 0x0401 +#define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 +#define LAN9303_MAC_RX_64_CNT_0 0x0411 +#define LAN9303_MAC_RX_127_CNT_0 0x0412 +#define LAN9303_MAC_RX_255_CNT_0 0x413 +#define LAN9303_MAC_RX_511_CNT_0 0x0414 +#define LAN9303_MAC_RX_1023_CNT_0 0x0415 +#define LAN9303_MAC_RX_MAX_CNT_0 0x0416 +#define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 +#define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 +#define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 +#define LAN9303_MAC_RX_MULCST_CNT_0 0x041a +#define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b +#define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c +#define LAN9303_MAC_RX_FRAG_CNT_0 0x041d +#define LAN9303_MAC_RX_JABB_CNT_0 0x041e +#define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f +#define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 +#define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 +#define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 +#define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 + +#define LAN9303_MAC_TX_CFG_0 0x0440 +#define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 +#define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 +#define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 +#define LAN9303_MAC_TX_64_CNT_0 0x0454 +#define LAN9303_MAC_TX_127_CNT_0 0x0455 +#define LAN9303_MAC_TX_255_CNT_0 0x0456 +#define LAN9303_MAC_TX_511_CNT_0 0x0457 +#define LAN9303_MAC_TX_1023_CNT_0 0x0458 +#define LAN9303_MAC_TX_MAX_CNT_0 0x0459 +#define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a +#define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c +#define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d +#define LAN9303_MAC_TX_MULCST_CNT_0 0x045e +#define LAN9303_MAC_TX_LATECOL_0 0x045f +#define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 +#define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 +#define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 +#define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 + +#define LAN9303_MAC_VER_ID_1 0x0800 +#define LAN9303_MAC_RX_CFG_1 0x0801 +#define LAN9303_MAC_TX_CFG_1 0x0840 +#define LAN9303_MAC_VER_ID_2 0x0c00 +#define LAN9303_MAC_RX_CFG_2 0x0c01 +#define LAN9303_MAC_TX_CFG_2 0x0c40 +#define LAN9303_SWE_ALR_CMD 0x1800 +#define LAN9303_SWE_VLAN_CMD 0x180b +# define LAN9303_SWE_VLAN_CMD_RNW BIT(5) +# define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) +#define LAN9303_SWE_VLAN_WR_DATA 0x180c +#define LAN9303_SWE_VLAN_RD_DATA 0x180e +# define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) +# define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) +# define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) +# define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) +# define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) +# define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) +#define LAN9303_SWE_VLAN_CMD_STS 0x1810 +#define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 +#define LAN9303_SWE_PORT_STATE 0x1843 +# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) +# define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) +# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) +# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) +# define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) +# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) +# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) +# define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) +# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) +#define LAN9303_SWE_PORT_MIRROR 0x1846 +# define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) +# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) +# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) +# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) +# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) +# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) +# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) +# define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) +# define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) +#define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 +#define LAN9303_BM_CFG 0x1c00 +#define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c +# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) +# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) +# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) + +static const struct regmap_range lan9303_valid_regs[] = { + regmap_reg_range(0x14, 0x17), /* misc, interrupt */ + regmap_reg_range(0x19, 0x19), /* endian test */ + regmap_reg_range(0x1d, 0x1d), /* hardware config */ + regmap_reg_range(0x23, 0x24), /* general purpose timer */ + regmap_reg_range(0x27, 0x27), /* counter */ + regmap_reg_range(0x29, 0x2a), /* PMI index regs */ + regmap_reg_range(0x68, 0x6a), /* flow control */ + regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ + regmap_reg_range(0x6d, 0x6f), /* misc */ + regmap_reg_range(0x70, 0x77), /* virtual phy */ + regmap_reg_range(0x78, 0x7a), /* GPIO */ + regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ + regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs */ +}; + +static const struct regmap_range lan9303_reserved_ranges[] = { + regmap_reg_range(0x00, 0x13), + regmap_reg_range(0x18, 0x18), + regmap_reg_range(0x1a, 0x1c), + regmap_reg_range(0x1e, 0x22), + regmap_reg_range(0x25, 0x26), + regmap_reg_range(0x28, 0x28), + regmap_reg_range(0x2b, 0x67), + regmap_reg_range(0x7b, 0x7b), + regmap_reg_range(0x7f, 0x7f), + regmap_reg_range(0xb8, 0xff), +}; + +const struct regmap_access_table lan9303_register_set = { + .yes_ranges = lan9303_valid_regs, + .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), + .no_ranges = lan9303_reserved_ranges, + .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), +}; + +static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) +{ + int ret; + + /* we can lose arbitration for the I2C case, because the device + * tries to detect and read an external EEPROM after reset and acts as + * a master on the shared I2C bus itself. This conflicts with our + * attempts to access the device as a slave at the same moment. + */ + do { + ret = regmap_read(regmap, offset, reg); + if (ret == -EAGAIN) + msleep(500); + } while (ret == -EAGAIN); + + return ret; +} + +/* virtual phy registers must be read mapped */ +static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) +{ + int ret; + u32 val; + + if (regnum > 7) + return -EINVAL; + + ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); + if (ret != 0) + return ret; + + return val & 0xffff; +} + +static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) +{ + if (regnum > 7) + return -EINVAL; + + return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); +} + +static int lan9303_port_phy_reg_wait_for_completion(struct lan9303 *chip) +{ + int ret; + u32 reg; + + /* transfer completed? */ + do { + ret = lan9303_read(chip->regmap, LAN9303_PMI_ACCESS, ®); + if (ret != 0) + return ret; + } while (reg & LAN9303_PMI_ACCESS_MII_BUSY); + + return 0; +} + +static int lan9303_port_phy_reg_read(struct lan9303 *chip, int addr, int regnum) +{ + int ret; + u32 val; + + val = ((unsigned int)addr) << 11; /* setup phy ID */ + val |= ((unsigned int)regnum) << 6; + + mutex_lock(&chip->indirect_mutex); + + ret = lan9303_port_phy_reg_wait_for_completion(chip); + if (ret != 0) + goto on_error; + + /* start the MII read cycle */ + ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); + if (ret != 0) + goto on_error; + + ret = lan9303_port_phy_reg_wait_for_completion(chip); + if (ret != 0) + goto on_error; + + /* read the result of this operation */ + ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); + if (ret != 0) + goto on_error; + + mutex_unlock(&chip->indirect_mutex); + + return val & 0xffff; + +on_error: + mutex_unlock(&chip->indirect_mutex); + return ret; +} + +static int lan9303_phy_reg_write(struct lan9303 *chip, int addr, int regnum, + unsigned int val) +{ + int ret; + u32 reg; + + reg = ((unsigned int)addr) << 11; /* setup phy ID */ + reg |= ((unsigned int)regnum) << 6; + reg |= LAN9303_PMI_ACCESS_MII_WRITE; + + mutex_lock(&chip->indirect_mutex); + + ret = lan9303_port_phy_reg_wait_for_completion(chip); + if (ret != 0) + goto on_error; + + /* write the data first... */ + ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); + if (ret != 0) + goto on_error; + + /* ...then start the MII write cycle */ + ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); + +on_error: + mutex_unlock(&chip->indirect_mutex); + return ret; +} + +static int lan9303_switch_wait_for_completion(struct lan9303 *chip) +{ + int ret; + u32 reg; + + /* transfer completed? */ + do { + ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_CMD, ®); + if (ret) { + dev_err(chip->dev, + "Failed to read csr command status: %d\n", + ret); + return ret; + } + } while (reg & LAN9303_SWITCH_CSR_CMD_BUSY); + + return 0; +} + +static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) +{ + u32 reg; + int ret; + + reg = regnum; + reg |= LAN9303_SWITCH_CSR_CMD_LANES; + reg |= LAN9303_SWITCH_CSR_CMD_BUSY; + + mutex_lock(&chip->indirect_mutex); + + ret = lan9303_switch_wait_for_completion(chip); + if (ret) + goto on_error; + + ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); + if (ret) { + dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); + goto on_error; + } + + /* trigger write */ + ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); + if (ret) + dev_err(chip->dev, "Failed to write csr command reg: %d\n", + ret); + +on_error: + mutex_unlock(&chip->indirect_mutex); + return ret; +} + +static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) +{ + u32 reg; + int ret; + + reg = regnum; + reg |= LAN9303_SWITCH_CSR_CMD_LANES; + reg |= LAN9303_SWITCH_CSR_CMD_RW; + reg |= LAN9303_SWITCH_CSR_CMD_BUSY; + + mutex_lock(&chip->indirect_mutex); + + ret = lan9303_switch_wait_for_completion(chip); + if (ret) + goto on_error; + + /* trigger read */ + ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); + if (ret) { + dev_err(chip->dev, "Failed to write csr command reg: %d\n", + ret); + goto on_error; + } + + ret = lan9303_switch_wait_for_completion(chip); + if (ret) + goto on_error; + + ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); + if (ret) + dev_err(chip->dev, "Failed to read csr data reg: %d\n", + ret); +on_error: + mutex_unlock(&chip->indirect_mutex); + return ret; +} + +static int lan9303_detect_phy_ids(struct lan9303 *chip) +{ + int reg; + + /* depending on the 'phy_addr_sel_strap' setting, the three phys are + * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the + * 'phy_addr_sel_strap' setting directly, so we need a test, which + * configuration is active: + * Register 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 + * and the IDs are 0-1-2, else it contains something different from + * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. + */ + reg = lan9303_port_phy_reg_read(chip, 3, 18); + if (reg < 0) { + dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); + return reg; + } + + if (reg != 0) + chip->phy_addr_sel_strap = 1; + else + chip->phy_addr_sel_strap = 0; + + dev_dbg(chip->dev, "Phy configuration '%s' detected\n", + chip->phy_addr_sel_strap ? "1-2-3" : "0-1-2"); + + return 0; +} + +static void lan9303_report_virt_phy_config(struct lan9303 *chip, + unsigned int reg) +{ + switch ((reg >> 8) & 0x03) { + case 0: + dev_info(chip->dev, "Virtual phy in 'MII MAC mode'\n"); + break; + case 1: + dev_info(chip->dev, "Virtual phy in 'MII PHY mode'\n"); + break; + case 2: + dev_info(chip->dev, "Virtual phy in 'RMII PHY mode'\n"); + break; + case 3: + dev_err(chip->dev, "Invalid virtual phy mode\n"); + break; + } + + if (reg & BIT(6)) + dev_info(chip->dev, "RMII clock is an output\n"); + else + dev_info(chip->dev, "RMII clock is an input\n"); +} + +/* stop processing packets at all ports */ +static int lan9303_disable_switching(struct lan9303 *chip) +{ + int ret; + + ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_0, 0x02); + if (ret) + return ret; + ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_1, 0x02); + if (ret) + return ret; + ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_2, 0x02); + if (ret) + return ret; + ret = lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_0, 0x56); + if (ret) + return ret; + ret = lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_1, 0x56); + if (ret) + return ret; + return lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_2, 0x56); +} + +/* start processing packets at CPU port */ +static int lan9303_enable_switching(struct lan9303 *chip) +{ + int ret; + + ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_0, 0x03); + if (ret) + return ret; + + return lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_0, 0x57); +} + +/* We want a special working switch: + * - do not route between port 1 and 2 + * - route everything from port 1 to port 0 + * - route everything from port 2 to port 0 + * - route special tagged packets from port 0 to port 1 *or* port 2 + */ +static int lan9303_separate_ports(struct lan9303 *chip) +{ + int ret; + + ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, + LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | + LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | + LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | + LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | + LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); + if (ret) + return ret; + + /* enable defining the destination port via special VLAN tagging + * for port 0 + */ + ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, + 0x03); + if (ret) + return ret; + + /* tag incoming packets at port 1 and 2 on their way to port 0 to be + * able to discover their source port + */ + ret = lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, + LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0); + if (ret) + return ret; + + /* prevent port 1 and 2 from forwarding packets by their own */ + return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, + LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | + LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | + LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); +} + +static int lan9303_handle_reset(struct lan9303 *chip) +{ + if (!chip->reset_gpio) + return 0; + + gpiod_export_link(chip->dev, "reset", chip->reset_gpio); + + if (chip->reset_duration != 0) + msleep(chip->reset_duration); + + /* release (deassert) reset and activate the device */ + gpiod_set_value_cansleep(chip->reset_gpio, 0); + + return 0; +} + +static int lan9303_check_device(struct lan9303 *chip) +{ + int ret; + u32 reg; + + ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); + if (ret) { + dev_err(chip->dev, "failed to read chip revision register: %d\n", + ret); +#ifdef DEBUG + if (!chip->reset_gpio) { + dev_warn(chip->dev, + "Maybe failed due to missing reset GPIO\n"); + } +#endif + return ret; + } + + if ((reg >> 16) != 0x9303) { + dev_err(chip->dev, "Invalid chip found: %X\n", reg >> 16); + return ret; + } + + /* The default state of the LAN9303 device is to forward packets between + * all ports (if not configured differently by an external EEPROM). + * The initial state of a DSA device must be forwarding packets only + * between the external and the internal ports and no forwarding + * between the external ports. In preparation we stop packet handling + * at all for now until the LAN9303 device is re-programmed accordingly. + */ + ret = lan9303_disable_switching(chip); + if (ret) + dev_warn(chip->dev, "failed to disable switching %d\n", ret); + + dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff); + + ret = lan9303_detect_phy_ids(chip); + if (ret) { + dev_err(chip->dev, "failed to discover phy bootstrap setup: %d\n", + ret); + return ret; + } + + ret = lan9303_read(chip->regmap, LAN9303_HW_CFG, ®); + if (ret) { + dev_err(chip->dev, "failed to detect hardware configuration %d\n", + ret); + return ret; + } + + if (reg & LAN9303_HW_CFG_AMDX_EN_PORT1) + dev_info(chip->dev, "Port 1 auto-dmx enabled\n"); + if (reg & LAN9303_HW_CFG_AMDX_EN_PORT2) + dev_info(chip->dev, "Port 2 auto-dmx enabled\n"); + + ret = lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ®); + if (ret < 0) + dev_err(chip->dev, "failed to read virtual phy configuration %d\n", + ret); + else + lan9303_report_virt_phy_config(chip, reg); + + ret = lan9303_read_switch_reg(chip, LAN9303_SW_DEV_ID, ®); + if (ret) { + dev_err(chip->dev, "failed to read switch device ID %d\n", ret); + return ret; + } + dev_info(chip->dev, "Switch device: %x, version %u, revision %u found\n", + (reg >> 16) & 0xff, (reg >> 8) & 0xff, reg & 0xff); + + ret = lan9303_read_switch_reg(chip, LAN9303_MAC_VER_ID_0, ®); + if (ret) { + dev_err(chip->dev, "failed to read switch MAC 0 ID %d\n", ret); + return ret; + } + dev_info(chip->dev, "MAC 0 device: %x, version %u, revision %u found\n", + (reg >> 8) & 0xf, (reg >> 4) & 0xf, reg & 0xf); + + ret = lan9303_read_switch_reg(chip, LAN9303_MAC_VER_ID_1, ®); + if (ret) { + dev_err(chip->dev, "failed to read switch MAC 1 ID %d\n", ret); + return ret; + } + dev_info(chip->dev, "MAC 1 device: %x, version %u, revision %u found\n", + (reg >> 8) & 0xf, (reg >> 4) & 0xf, reg & 0xf); + + ret = lan9303_read_switch_reg(chip, LAN9303_MAC_VER_ID_2, ®); + if (ret) { + dev_err(chip->dev, "failed to read switch MAC 2 ID %d\n", ret); + return ret; + } + dev_info(chip->dev, "MAC 2 device: %x, version %u, revision %u found\n", + (reg >> 8) & 0xf, (reg >> 4) & 0xf, reg & 0xf); + + return 0; +} + +/* ---------------------------- DSA -----------------------------------*/ + +static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds) +{ + return DSA_TAG_PROTO_LAN9303; +} + +static int lan9303_setup(struct dsa_switch *ds) +{ + struct lan9303 *chip = ds_to_lan9303(ds); + int ret; + + /* Make sure that port 0 is the cpu port */ + if (!dsa_is_cpu_port(ds, 0)) { + dev_err(chip->dev, "port 0 is not the CPU port\n"); + return -EINVAL; + } + + ret = lan9303_separate_ports(chip); + if (ret) + dev_err(chip->dev, "failed to separate ports %d\n", ret); + + ret = lan9303_enable_switching(chip); + if (ret) + dev_err(chip->dev, "failed to re-enable switching %d\n", ret); + + return 0; +} + +struct lan9303_mib_desc { + unsigned int offset; /* offset of first MAC */ + const char *name; +}; + +static const struct lan9303_mib_desc lan9303_mib[] = { + { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, + { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, + { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, + { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, + { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, + { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, + { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, + { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, + { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, + { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, + { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, + { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, + { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, + { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, + { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, + { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, + { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, + { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, + { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, + { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, + { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, + { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, + { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", }, + { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, + { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, + { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, + { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, + { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, + { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, + { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, + { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, + { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, + { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, + { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, + { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, + { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, + { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, +}; + +static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data) +{ + unsigned int u; + + for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { + strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name, + ETH_GSTRING_LEN); + } +} + +static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum) +{ + struct lan9303 *chip = ds_to_lan9303(ds); + int phy_base = chip->phy_addr_sel_strap; + + if (phy == phy_base) + return lan9303_virt_phy_reg_read(chip, regnum); + if (phy > phy_base + 2) + return -ENODEV; + + return lan9303_port_phy_reg_read(chip, phy, regnum); +} + +static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum, + u16 val) +{ + struct lan9303 *chip = ds_to_lan9303(ds); + int phy_base = chip->phy_addr_sel_strap; + + if (phy == phy_base) + return lan9303_virt_phy_reg_write(chip, regnum, val); + if (phy > phy_base + 2) + return -ENODEV; + + return lan9303_phy_reg_write(chip, phy, regnum, val); +} + +static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct lan9303 *chip = ds_to_lan9303(ds); + u32 reg; + unsigned int u, poff; + int ret; + + dev_dbg(chip->dev, "%s called\n", __func__); + + poff = port * 0x400; + + for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { + ret = lan9303_read_switch_reg(chip, + lan9303_mib[u].offset + poff, + ®); + if (ret != 0) + dev_warn(chip->dev, "Reading status reg %u failed\n", + lan9303_mib[u].offset + poff); + data[u] = reg; + } +} + +/* ethtool function used to query the number of statistics items */ +static int lan9303_get_sset_count(struct dsa_switch *ds) +{ + return ARRAY_SIZE(lan9303_mib); +} + +/* power on the given port */ +static int lan9303_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phy) +{ + struct lan9303 *chip = ds_to_lan9303(ds); + int rc; + + /* enable internal data handling */ + switch (port) { + case 1: + rc = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_1, 0x03); + rc += lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_1, + 0x57); + break; + case 2: + rc = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_2, 0x03); + rc += lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_2, + 0x57); + break; + default: + dev_dbg(chip->dev, "Error: request to power up invalid port %d\n", + port); + return -ENODEV; + } + + return rc; +} + +static void lan9303_port_disable(struct dsa_switch *ds, int port, + struct phy_device *phy) +{ + struct lan9303 *chip = ds_to_lan9303(ds); + int rc; + + /* disable internal data handling */ + switch (port) { + case 1: + rc = lan9303_phy_reg_write(chip, chip->phy_addr_sel_strap + 1, + 0, BIT(14) | BIT(11)); + rc += lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_1, + 0x02); + rc += lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_1, + 0x56); + break; + case 2: + rc = lan9303_phy_reg_write(chip, chip->phy_addr_sel_strap + 2, + 0, BIT(14) | BIT(11)); + rc += lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_2, + 0x02); + rc += lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_2, + 0x56); + break; + default: + dev_dbg(chip->dev, "Error: request to power down invalid port %d\n", + port); + } +} + +static struct dsa_switch_ops lan9303_switch_ops = { + .get_tag_protocol = lan9303_get_tag_protocol, + .setup = lan9303_setup, + .get_strings = lan9303_get_strings, + .phy_read = lan9303_phy_read, + .phy_write = lan9303_phy_write, + .get_ethtool_stats = lan9303_get_ethtool_stats, + .get_sset_count = lan9303_get_sset_count, + .port_enable = lan9303_port_enable, + .port_disable = lan9303_port_disable, +}; + +static int lan9303_register_phys(struct lan9303 *chip) +{ + chip->ds.priv = chip; + chip->ds.dev = chip->dev; + chip->ds.ops = &lan9303_switch_ops; + chip->ds.phys_mii_mask = chip->phy_addr_sel_strap ? 0xe : 0x7; + + return dsa_register_switch(&chip->ds, chip->dev); +} + +static void lan9303_probe_reset_gpio(struct lan9303 *chip, + struct device_node *np) +{ + chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "phy-reset", + GPIOD_OUT_LOW); + + if (!chip->reset_gpio) { + dev_dbg(chip->dev, "No reset GPIO defined\n"); + return; + } + + chip->reset_duration = 200; + + if (np) { + of_property_read_u32(np, "phy-reset-duration", + &chip->reset_duration); + } else { + dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); + } + + /* A sane reset duration should not be longer than 1s */ + if (chip->reset_duration > 1000) + chip->reset_duration = 1000; +} + +int lan9303_probe(struct lan9303 *chip, struct device_node *np) +{ + int ret; + + mutex_init(&chip->indirect_mutex); + + lan9303_probe_reset_gpio(chip, np); + + ret = lan9303_handle_reset(chip); + if (ret != 0) + return ret; + + ret = lan9303_check_device(chip); + if (ret != 0) + return ret; + + ret = lan9303_register_phys(chip); + if (ret != 0) + return ret; + + return 0; +} + +int lan9303_remove(struct lan9303 *chip) +{ + int rc; + + rc = lan9303_disable_switching(chip); + if (rc != 0) + dev_warn(chip->dev, "shutting down failed\n"); + + dsa_unregister_switch(&chip->ds); + + /* assert reset to the whole device to prevent it from doing anything */ + gpiod_set_value_cansleep(chip->reset_gpio, 1); + gpiod_unexport(chip->reset_gpio); + + return 0; +} + +MODULE_AUTHOR("Juergen Borleis "); +MODULE_DESCRIPTION("Driver for SMSC/Microchip LAN9303 three port ethernet switch"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/phy/lan9303.h b/drivers/net/phy/lan9303.h new file mode 100644 index 0000000000000..cfb1c5d5fef51 --- /dev/null +++ b/drivers/net/phy/lan9303.h @@ -0,0 +1,21 @@ +#include +#include +#include + +struct lan9303 { + struct device *dev; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data; + struct gpio_desc *reset_gpio; + u32 reset_duration; /* in [ms] */ + bool phy_addr_sel_strap; + struct dsa_switch ds; + struct mutex indirect_mutex; /* protect indexed register access */ +}; + +extern const struct regmap_access_table lan9303_register_set; + +#define ds_to_lan9303(dsasw) container_of(dsasw, struct lan9303, ds) + +int lan9303_probe(struct lan9303 *chip, struct device_node *np); +int lan9303_remove(struct lan9303 *chip); -- 2.11.0