Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933735AbdDELOY (ORCPT ); Wed, 5 Apr 2017 07:14:24 -0400 Received: from mga06.intel.com ([134.134.136.31]:18820 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755033AbdDELNe (ORCPT ); Wed, 5 Apr 2017 07:13:34 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,278,1486454400"; d="scan'208";a="1151356725" Date: Wed, 5 Apr 2017 14:12:58 +0300 From: "Kirill A. Shutemov" To: Denys Vlasenko Cc: brgerst@gmail.com, torvalds@linux-foundation.org, akpm@linux-foundation.org, luto@amacapital.net, linux-kernel@vger.kernel.org, jpoimboe@redhat.com, luto@kernel.org, peterz@infradead.org, bp@alien8.de, hpa@zytor.com, dave.hansen@intel.com, tglx@linutronix.de, mingo@kernel.org, linux-tip-commits@vger.kernel.org Subject: Re: [tip:x86/mm] x86/asm: Remove __VIRTUAL_MASK_SHIFT==47 assert Message-ID: <20170405111258.5ro7momzscweinuf@black.fi.intel.com> References: <20170330080731.65421-3-kirill.shutemov@linux.intel.com> <53f40ad7-2775-517f-91d1-bde811697045@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <53f40ad7-2775-517f-91d1-bde811697045@redhat.com> User-Agent: NeoMutt/20161126 (1.7.0) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2526 Lines: 64 On Tue, Apr 04, 2017 at 05:36:33PM +0200, Denys Vlasenko wrote: > > diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S > > index 044d18e..f07b4ef 100644 > > --- a/arch/x86/entry/entry_64.S > > +++ b/arch/x86/entry/entry_64.S > > @@ -265,12 +265,9 @@ return_from_SYSCALL_64: > > * > > * If width of "canonical tail" ever becomes variable, this will need > > * to be updated to remain correct on both old and new CPUs. > > + * > > + * Change top 16 bits to be the sign-extension of 47th bit > > The comment above stops being correct: it's not necessary 16 top bits > we sign-extend now. With larger __VIRTUAL_MASK_SHIFT for 5-level translation, > it will become 7 bits (if I do the math right). Does the patch below look okay to you? > > */ > > - .ifne __VIRTUAL_MASK_SHIFT - 47 > > - .error "virtual address width changed -- SYSRET checks need update" > > - .endif > > - > > - /* Change top 16 bits to be the sign-extension of 47th bit */ > > shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx > > sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx > > The bigger problem here would be the future boot-time choice of 4/5-level > page tables: __VIRTUAL_MASK_SHIFT will need to depend on that choice, > but in this location it is preferable to not use any variables > (memory references). Yeah. Will see what I will be able to come up with. Not sure yet. -------------------8<---------------------- >From 2433cf4f8847bbc41cc2b02d6af4f191b3b5a0c5 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Wed, 5 Apr 2017 14:06:15 +0300 Subject: [PATCH] x86/asm: Fix comment in return_from_SYSCALL_64 On x86-64 __VIRTUAL_MASK_SHIFT depends on paging mode now. Signed-off-by: Kirill A. Shutemov --- arch/x86/entry/entry_64.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 607d72c4a485..c70e064d9592 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -266,7 +266,8 @@ return_from_SYSCALL_64: * If width of "canonical tail" ever becomes variable, this will need * to be updated to remain correct on both old and new CPUs. * - * Change top 16 bits to be the sign-extension of 47th bit + * Change top bits to match most significant valuable bit (47 or 56 + * depending on paging mode) in the address. */ shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx -- Kirill A. Shutemov