Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755669AbdDEOeW (ORCPT ); Wed, 5 Apr 2017 10:34:22 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:14605 "EHLO nat-hk.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753243AbdDEOcW (ORCPT ); Wed, 5 Apr 2017 10:32:22 -0400 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Wed, 05 Apr 2017 07:32:19 -0700 From: Laxman Dewangan To: , , CC: , , , , , Laxman Dewangan Subject: [PATCH 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Date: Wed, 5 Apr 2017 19:43:42 +0530 Message-ID: <1491401626-31303-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 722 Lines: 19 This patch series have following fixes: - Add more precession in PWM period register value calculation for lower pwm frequency. - Add support to configure PWM pins in different state in the suspend/resume. Laxman Dewangan (4): pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation pwm: tegra: Increase precision in pwm rate calculation pwm: tegra: Add DT binding details to configure pin in suspends/resume pwm: tegra: Add support to configure pin state in suspends/resume .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++ drivers/pwm/pwm-tegra.c | 77 ++++++++++++++++++++-- 2 files changed, 116 insertions(+), 4 deletions(-) -- 2.1.4