Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753473AbdDFISW (ORCPT ); Thu, 6 Apr 2017 04:18:22 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16524 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751475AbdDFISS (ORCPT ); Thu, 6 Apr 2017 04:18:18 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 06 Apr 2017 01:18:17 -0700 From: Mikko Perttunen To: , , CC: , , , Matt Craighead , Mikko Perttunen Subject: [PATCH] irqchip/gic: Don't write to GICD_ICFGR0 Date: Thu, 6 Apr 2017 11:17:11 +0300 Message-ID: <1491466631-11206-1-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1244 Lines: 37 From: Matt Craighead According to the GICv2 specification, the GICD_ICFGR0, or GIC_DIST_CONFIG[0] register is read-only. Therefore avoid writing to it. Signed-off-by: Matt Craighead [mperttunen@nvidia.com: commit message rewritten] Signed-off-by: Mikko Perttunen --- drivers/irqchip/irq-gic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 1b1df4f770bd..d9c0000050e0 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -609,7 +609,7 @@ void gic_dist_restore(struct gic_chip_data *gic) writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) + for (i = 1; i < DIV_ROUND_UP(gic_irqs, 16); i++) writel_relaxed(gic->saved_spi_conf[i], dist_base + GIC_DIST_CONFIG + i * 4); @@ -699,7 +699,7 @@ void gic_cpu_restore(struct gic_chip_data *gic) } ptr = raw_cpu_ptr(gic->saved_ppi_conf); - for (i = 0; i < DIV_ROUND_UP(32, 16); i++) + for (i = 1; i < DIV_ROUND_UP(32, 16); i++) writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); for (i = 0; i < DIV_ROUND_UP(32, 4); i++) -- 2.1.4