Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935400AbdDFOmR (ORCPT ); Thu, 6 Apr 2017 10:42:17 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3579 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755664AbdDFOmI (ORCPT ); Thu, 6 Apr 2017 10:42:08 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 06 Apr 2017 07:42:08 -0700 From: Laxman Dewangan To: , , CC: , , , , , Laxman Dewangan Subject: [PATCH V2 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Date: Thu, 6 Apr 2017 19:50:57 +0530 Message-ID: <1491488461-24621-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 829 Lines: 23 This patch series have following fixes: - Add more precession in PWM period register value calculation for lower pwm frequency. - Add support to configure PWM pins in different state in the suspend/resume. Changes from v1: - Use standard pinctrl names for sleep and active state. - Use API pinctrl_pm_select_*() Laxman Dewangan (4): pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation pwm: tegra: Increase precision in pwm rate calculation pwm: tegra: Add DT binding details to configure pin in suspends/resume pwm: tegra: Add support to configure pin state in suspends/resume .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++ drivers/pwm/pwm-tegra.c | 77 ++++++++++++++++++++-- 2 files changed, 116 insertions(+), 4 deletions(-) -- 2.1.4