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Date: Thu, 6 Apr 2017 16:27:00 -0400
From: Jerome Glisse <jglisse@redhat.com>
To: Wu Hao <hao.wu@intel.com>
Cc: atull@kernel.org, moritz.fischer@ettus.com, linux-fpga@vger.kernel.org,
        linux-kernel@vger.kernel.org, luwei.kang@intel.com,
        yi.z.zhang@intel.com
Subject: Re: [PATCH 00/16] Intel FPGA Device Drivers
Message-ID: <20170406202700.GA3674@redhat.com>
References: <1490875696-15145-1-git-send-email-hao.wu@intel.com>
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On Thu, Mar 30, 2017 at 08:08:00PM +0800, Wu Hao wrote:
> Hi All,
> 
> Here is a patch-series adding drivers for Intel FPGA devices.
> 
> The Intel FPGA driver provides interfaces for userspace applications to
> configure, enumerate, open, and access FPGA accelerators on platforms
> equipped with Intel(R) FPGA solutions and enables system level management
> functions such as FPGA partial reconfiguration, power management and
> virtualization.
> 
> This patch series only adds the basic functions for FPGA accelerators and
> partial reconfiguration. Patches for more functions, e.g power management
> and virtualization, will be submitted after this series gets reviewed.
> 
> Patch 1: add a document for Intel FPGA driver overview, including the HW
> architecture, driver organization, device enumeration, virtualization and
> opens.
> 
> Patch 2: introduce a fpga-dev class. It's used in below Intel FPGA PCIe
> device driver, to represent a FPGA device on the system, and all actual
> feature devices should be registered as child nodes of this container
> fpga-dev device.
> 
> Patch 3-7: implement Intel FPGA PCIe device driver. It walks through the
> 'Device Feature List' in the PCI Bar, creates the container fpga-dev as
> parent and platform devices as children for the feature devices it found.
> 
> Patch 8-11: implement Intel FPGA Management Engine (FME) driver. It's a
> platform driver matching with the FME platform device created by above
> PCIe driver. Sysfs and device file ioctls are exposed as user interfaces
> to allow partial reconfiguration to Accelerated Function Units (AFUs) from
> user space applications.

Do we have an open source toolchain to generate the FPGA configuration
(bitstream) ? As it is required for the GPU sub-system that any driver
API must comes with open source userspace.

Or are FPGA given a free pass ?


Cheers,
J?r?me