Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756340AbdDGJww (ORCPT ); Fri, 7 Apr 2017 05:52:52 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:31107 "EHLO nat-hk.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756202AbdDGJwl (ORCPT ); Fri, 7 Apr 2017 05:52:41 -0400 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Fri, 07 Apr 2017 02:52:39 -0700 From: Laxman Dewangan To: , , CC: , , , , , Laxman Dewangan Subject: [PATCH V3 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Date: Fri, 7 Apr 2017 15:03:58 +0530 Message-ID: <1491557642-15940-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 928 Lines: 27 This patch series have following fixes: - Add more precession in PWM period register value calculation for lower pwm frequency. - Add support to configure PWM pins in different state in the suspend/resume. Changes from v1: - Use standard pinctrl names for sleep and active state. - Use API pinctrl_pm_select_*() Changes from V2: - Type fixes, rephrases commit message and use pinctrl_pm_state* return value. Laxman Dewangan (4): pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation pwm: tegra: Increase precision in pwm rate calculation pwm: tegra: Add DT binding details to configure pin in suspends/resume pwm: tegra: Add support to configure pin state in suspends/resume .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++ drivers/pwm/pwm-tegra.c | 77 ++++++++++++++++++++-- 2 files changed, 116 insertions(+), 4 deletions(-) -- 2.1.4