Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753029AbdDKPOH (ORCPT ); Tue, 11 Apr 2017 11:14:07 -0400 Received: from smtp5-g21.free.fr ([212.27.42.5]:56281 "EHLO smtp5-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752164AbdDKPOD (ORCPT ); Tue, 11 Apr 2017 11:14:03 -0400 Subject: Re: [RFC PATCH v0.2] PCI: Add support for tango PCIe host bridge To: Marc Zyngier , Thomas Gleixner Cc: Bjorn Helgaas , Robin Murphy , Lorenzo Pieralisi , Liviu Dudau , David Laight , linux-pci , Linux ARM , Thibaud Cornic , Phuong Nguyen , LKML References: <91db1f47-3024-9712-309a-fb4b21e42028@free.fr> <310db9dd-7db6-2106-2e53-f0083b2d3758@free.fr> <012f7fcb-eaeb-70dd-a1a9-06c213789d30@arm.com> <0502e180-5517-12d6-e3a1-bcea0da7e201@free.fr> <4edd799a-650c-0189-cd5c-e9fc18c5f8bc@arm.com> From: Mason Message-ID: <30f662a6-5dab-515b-e35a-a312f3c7b509@free.fr> Date: Tue, 11 Apr 2017 17:13:35 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:51.0) Gecko/20100101 Firefox/51.0 SeaMonkey/2.48 MIME-Version: 1.0 In-Reply-To: <4edd799a-650c-0189-cd5c-e9fc18c5f8bc@arm.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1430 Lines: 42 On 27/03/2017 19:09, Marc Zyngier wrote: > Here's what your system looks like: > > PCI-EP -------> MSI Controller ------> INTC > MSI IRQ > > A PCI MSI is always edge. No ifs, no buts. That's what it is, and nothing > else. Now, your MSI controller signals its output using a level interrupt, > since you need to whack it on the head so that it lowers its line. > > There is not a single trigger, because there is not a single interrupt. Hello Marc, I was hoping you or Thomas might help clear some confusion in my mind around IRQ domains (struct irq_domain). I have read https://www.kernel.org/doc/Documentation/IRQ-domain.txt IIUC, there should be one IRQ domain per IRQ controller. I have this MSI controller handling 256 interrupts, so I should have *one* domain for all possible MSIs. Yet the Altera driver registers *two* domains (msi_domain and inner_domain). Could I make everything work with a single IRQ domain? I'm confused by the sequence: irq_dom = irq_domain_create_linear(fwnode, MSI_COUNT, &msi_dom_ops, pcie); msi_dom = pci_msi_create_irq_domain(fwnode, &msi_domain_info, irq_dom); It seems I should be able to call only pci_msi_create_irq_domain... And the parent of the MSI controller is given in the DT. I'm not quite sure how I tell pci_msi_create_irq_domain how many MSIs it's supposed to manage. Nor how I pass my private struct. I will keep looking. Regards.