Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755541AbdDLU5u (ORCPT ); Wed, 12 Apr 2017 16:57:50 -0400 Received: from 1.mo178.mail-out.ovh.net ([178.33.251.53]:39916 "EHLO 1.mo178.mail-out.ovh.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754675AbdDLU5s (ORCPT ); Wed, 12 Apr 2017 16:57:48 -0400 Subject: Re: [PATCH v1 1/1] mtd: mtk-nor: set controller's address width according to nor flash To: Guochun Mao , Cyrille Pitchen References: <1491381462-21893-1-git-send-email-guochun.mao@mediatek.com> <1491381462-21893-2-git-send-email-guochun.mao@mediatek.com> Cc: Mark Rutland , devicetree@vger.kernel.org, Richard Weinberger , Russell King , linux-kernel@vger.kernel.org, Rob Herring , linux-mtd@lists.infradead.org, Matthias Brugger , linux-mediatek@lists.infradead.org, David Woodhouse , linux-arm-kernel@lists.infradead.org From: Cyrille Pitchen Message-ID: Date: Wed, 12 Apr 2017 22:57:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <1491381462-21893-2-git-send-email-guochun.mao@mediatek.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit X-Ovh-Tracer-Id: 10719974489204217852 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeigdduheehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2032 Lines: 70 Hi Guochun, Le 05/04/2017 ? 10:37, Guochun Mao a ?crit : > When nor's size larger than 16MByte, nor's address width maybe > set to 3 or 4, and controller should change address width according > to nor's setting. > > Signed-off-by: Guochun Mao > --- > drivers/mtd/spi-nor/mtk-quadspi.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c > index e661877..b637770 100644 > --- a/drivers/mtd/spi-nor/mtk-quadspi.c > +++ b/drivers/mtd/spi-nor/mtk-quadspi.c > @@ -104,6 +104,8 @@ > #define MTK_NOR_MAX_RX_TX_SHIFT 6 > /* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */ > #define MTK_NOR_MAX_SHIFT 7 > +/* nor controller 4-byte address mode enable bit */ > +#define MTK_NOR_4B_ADDR_EN BIT(4) > > /* Helpers for accessing the program data / shift data registers */ > #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n)) > @@ -230,10 +232,35 @@ static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor) > 10000); > } > > +static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor) > +{ > + u8 val; > + struct spi_nor *nor = &mt8173_nor->nor; > + > + val = readb(mt8173_nor->base + MTK_NOR_DUAL_REG); > + > + switch (nor->addr_width) { > + case 3: > + val &= ~MTK_NOR_4B_ADDR_EN; > + break; > + case 4: > + val |= MTK_NOR_4B_ADDR_EN; > + break; > + default: > + dev_warn(mt8173_nor->dev, "Unexpected address width %u.\n", > + nor->addr_width); > + break; > + } > + > + writeb(val, mt8173_nor->base + MTK_NOR_DUAL_REG); > +} > + > static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr) > { > int i; > > + mt8173_nor_set_addr_width(mt8173_nor); > + > for (i = 0; i < 3; i++) { Should it be 'i < nor->addr_width' instead of 'i < 3' ? Does it work when accessing data after 128Mbit ? Best regards, Cyrille > writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4); > addr >>= 8; >