Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754003AbdDNJhM (ORCPT ); Fri, 14 Apr 2017 05:37:12 -0400 Received: from terminus.zytor.com ([65.50.211.136]:44951 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751528AbdDNJhJ (ORCPT ); Fri, 14 Apr 2017 05:37:09 -0400 Date: Fri, 14 Apr 2017 02:31:30 -0700 From: tip-bot for Kan Liang Message-ID: Cc: tglx@linutronix.de, kan.liang@intel.com, peterz@infradead.org, alexander.shishkin@linux.intel.com, jolsa@redhat.com, torvalds@linux-foundation.org, hpa@zytor.com, acme@redhat.com, eranian@google.com, linux-kernel@vger.kernel.org, vincent.weaver@maine.edu, mingo@kernel.org Reply-To: linux-kernel@vger.kernel.org, eranian@google.com, mingo@kernel.org, vincent.weaver@maine.edu, tglx@linutronix.de, alexander.shishkin@linux.intel.com, peterz@infradead.org, kan.liang@intel.com, jolsa@redhat.com, acme@redhat.com, torvalds@linux-foundation.org, hpa@zytor.com In-Reply-To: <1491333246-3965-1-git-send-email-kan.liang@intel.com> References: <1491333246-3965-1-git-send-email-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86: Fix spurious NMI with PEBS Load Latency event Git-Commit-ID: fd583ad1563bec5f00140e1f2444adbcd331caad X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3661 Lines: 95 Commit-ID: fd583ad1563bec5f00140e1f2444adbcd331caad Gitweb: http://git.kernel.org/tip/fd583ad1563bec5f00140e1f2444adbcd331caad Author: Kan Liang AuthorDate: Tue, 4 Apr 2017 15:14:06 -0400 Committer: Ingo Molnar CommitDate: Fri, 14 Apr 2017 10:31:39 +0200 perf/x86: Fix spurious NMI with PEBS Load Latency event Spurious NMIs will be observed with the following command: while :; do perf record -bae "cpu/umask=0x01,event=0xcd,ldlat=0x80/pp" -e "cpu/umask=0x03,event=0x0/" -e "cpu/umask=0x02,event=0x0/" -e cycles,branches,cache-misses -e cache-references -- sleep 10 done The bug was introduced by commit: 8077eca079a2 ("perf/x86/pebs: Add workaround for broken OVFL status on HSW+") That commit clears the status bits for the counters used for PEBS events, by masking the whole 64 bits pebs_enabled. However, only the low 32 bits of both status and pebs_enabled are reserved for PEBS-able counters. For status bits 32-34 are fixed counter overflow bits. For pebs_enabled bits 32-34 are for PEBS Load Latency. In the test case, the PEBS Load Latency event and fixed counter event could overflow at the same time. The fixed counter overflow bit will be cleared by mistake. Once it is cleared, the fixed counter overflow never be processed, which finally trigger spurious NMI. Correct the PEBS enabled mask by ignoring the non-PEBS bits. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Fixes: 8077eca079a2 ("perf/x86/pebs: Add workaround for broken OVFL status on HSW+") Link: http://lkml.kernel.org/r/1491333246-3965-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/core.c | 2 +- arch/x86/events/intel/ds.c | 2 +- arch/x86/events/perf_event.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4244bed..a6d91d4 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2151,7 +2151,7 @@ again: * counters from the GLOBAL_STATUS mask and we always process PEBS * events via drain_pebs(). */ - status &= ~cpuc->pebs_enabled; + status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); /* * PEBS overflow sets bit 62 in the global status register diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 9dfeeec..c6d23ff 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1222,7 +1222,7 @@ get_next_pebs_record_by_bit(void *base, void *top, int bit) /* clear non-PEBS bit and re-check */ pebs_status = p->status & cpuc->pebs_enabled; - pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1; + pebs_status &= PEBS_COUNTER_MASK; if (pebs_status == (1 << bit)) return at; } diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index bcbb1d2..be3d362 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -79,6 +79,7 @@ struct amd_nb { /* The maximal number of PEBS events: */ #define MAX_PEBS_EVENTS 8 +#define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) /* * Flags PEBS can handle without an PMI.