Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753877AbdDNOUe (ORCPT ); Fri, 14 Apr 2017 10:20:34 -0400 Received: from terminus.zytor.com ([65.50.211.136]:45577 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752189AbdDNOUc (ORCPT ); Fri, 14 Apr 2017 10:20:32 -0400 Date: Fri, 14 Apr 2017 07:19:17 -0700 From: tip-bot for Vikas Shivappa Message-ID: Cc: hpa@zytor.com, linux-kernel@vger.kernel.org, mingo@kernel.org, vikas.shivappa@linux.intel.com, tglx@linutronix.de Reply-To: linux-kernel@vger.kernel.org, hpa@zytor.com, tglx@linutronix.de, vikas.shivappa@linux.intel.com, mingo@kernel.org In-Reply-To: <1491611637-20417-4-git-send-email-vikas.shivappa@linux.intel.com> References: <1491611637-20417-4-git-send-email-vikas.shivappa@linux.intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/cpu] x86/intel_rdt/mba: Memory bandwith allocation feature detect Git-Commit-ID: ab66a33b032eb5b8186aeaf648127bce829c9efd X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3328 Lines: 87 Commit-ID: ab66a33b032eb5b8186aeaf648127bce829c9efd Gitweb: http://git.kernel.org/tip/ab66a33b032eb5b8186aeaf648127bce829c9efd Author: Vikas Shivappa AuthorDate: Fri, 7 Apr 2017 17:33:52 -0700 Committer: Thomas Gleixner CommitDate: Fri, 14 Apr 2017 16:10:07 +0200 x86/intel_rdt/mba: Memory bandwith allocation feature detect Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1. Add supporting data structures to detect feature details which is done in later patch using CPUID with EAX=10H, ECX= 3. Signed-off-by: Vikas Shivappa Cc: ravi.v.shankar@intel.com Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com Cc: vikas.shivappa@intel.com Link: http://lkml.kernel.org/r/1491611637-20417-4-git-send-email-vikas.shivappa@linux.intel.com Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/cpufeatures.h | 2 ++ arch/x86/include/asm/intel_rdt.h | 8 ++++++++ arch/x86/kernel/cpu/intel_rdt.c | 4 ++++ arch/x86/kernel/cpu/scattered.c | 1 + 4 files changed, 15 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b04bb6d..25d7f52 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -201,6 +201,8 @@ #define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ #define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ +#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ + /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h index 51e4a1c..6295594 100644 --- a/arch/x86/include/asm/intel_rdt.h +++ b/arch/x86/include/asm/intel_rdt.h @@ -184,6 +184,14 @@ union cpuid_0x10_1_eax { unsigned int full; }; +/* CPUID.(EAX=10H, ECX=ResID=3).EAX */ +union cpuid_0x10_3_eax { + struct { + unsigned int max_delay:12; + } split; + unsigned int full; +}; + /* CPUID.(EAX=10H, ECX=ResID).EDX */ union cpuid_0x10_x_edx { struct { diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c index 8486abe..82eafd6 100644 --- a/arch/x86/kernel/cpu/intel_rdt.c +++ b/arch/x86/kernel/cpu/intel_rdt.c @@ -430,6 +430,10 @@ static __init bool get_rdt_resources(void) rdt_get_cache_config(2, &rdt_resources_all[RDT_RESOURCE_L2]); ret = true; } + + if (boot_cpu_has(X86_FEATURE_MBA)) + ret = true; + return ret; } diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index d979406..23c2350 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 }, { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 }, + { X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 }, { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },