Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934744AbdDSOMH (ORCPT ); Wed, 19 Apr 2017 10:12:07 -0400 Received: from foss.arm.com ([217.140.101.70]:40600 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934727AbdDSOME (ORCPT ); Wed, 19 Apr 2017 10:12:04 -0400 Subject: Re: [PATCH v3 5/7] ARM: NOMMU: Introduce dma operations for noMMU To: Arnd Bergmann References: <1489137839-549-1-git-send-email-vladimir.murzin@arm.com> <1489137839-549-6-git-send-email-vladimir.murzin@arm.com> Cc: Linux ARM , Alexandre Torgue , Russell King - ARM Linux , Linux Kernel Mailing List , kbuild-all@01.org, Benjamin Gaignard , Andrew Morton , Robin Murphy , sza@esh.hu From: Vladimir Murzin Message-ID: Date: Wed, 19 Apr 2017 15:12:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2206 Lines: 49 On 19/04/17 11:10, Arnd Bergmann wrote: > On Fri, Mar 10, 2017 at 10:23 AM, Vladimir Murzin > wrote: >> R/M classes of cpus can have memory covered by MPU which in turn might >> configure RAM as Normal i.e. bufferable and cacheable. It breaks >> dma_alloc_coherent() and friends, since data can stuck in caches now >> or be buffered. >> >> This patch factors out DMA support for NOMMU configuration into >> separate entity which provides dedicated dma_ops. We have to handle >> there several cases: >> - configurations with MMU/MPU setup >> - configurations without MMU/MPU setup >> - special case for M-class, since caches and MPU there are optional >> >> In general we rely on default DMA area for coherent allocations or/and >> per-device memory reserves suitable for coherent DMA, so if such >> regions are set coherent allocations go from there. >> >> In case MPU/MPU was not setup we fallback to normal page allocator for >> DMA memory allocation. >> >> In case we run M-class cpus, for configuration without cache support >> (like Cortex-M3/M4) dma operations are forced to be coherent and wired >> with dma-noop (such decision is made based on cacheid global >> variable); however, if caches are detected there and no DMA coherent >> region is given (either default or per-device), dma is disallowed even >> MPU is not set - it is because M-class implement system memory map >> which defines part of address space as Normal memory. >> >> Reported-by: Alexandre Torgue >> Reported-by: Andras Szemzo >> Tested-by: Benjamin Gaignard >> Tested-by: Andras Szemzo >> Tested-by: Alexandre TORGUE >> Reviewed-by: Robin Murphy >> Signed-off-by: Vladimir Murzin > > I thought I found a couple of problems with this, but after reading more > carefully I was wrong about all of them and I think the code is doing > exactly the right thing. I also like the way this is split out into a separate > set of dma_map_ops to simplify the normal MMU case. > > Acked-by: Arnd Bergmann > Much appreciated! Vladimir