Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032357AbdDTOM0 (ORCPT ); Thu, 20 Apr 2017 10:12:26 -0400 Received: from terminus.zytor.com ([65.50.211.136]:57283 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032341AbdDTOMX (ORCPT ); Thu, 20 Apr 2017 10:12:23 -0400 Date: Thu, 20 Apr 2017 07:09:51 -0700 From: tip-bot for Paul Burton Message-ID: Cc: marc.zyngier@arm.com, tglx@linutronix.de, hpa@zytor.com, jason@lakedaemon.net, matt.redfearn@imgtec.com, ralf@linux-mips.org, linux-kernel@vger.kernel.org, mingo@kernel.org, paul.burton@imgtec.com Reply-To: jason@lakedaemon.net, hpa@zytor.com, tglx@linutronix.de, marc.zyngier@arm.com, mingo@kernel.org, paul.burton@imgtec.com, linux-kernel@vger.kernel.org, matt.redfearn@imgtec.com, ralf@linux-mips.org In-Reply-To: <1492679256-14513-2-git-send-email-matt.redfearn@imgtec.com> References: <1492679256-14513-2-git-send-email-matt.redfearn@imgtec.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:irq/core] irqchip/mips-gic: Separate IPI reservation & usage tracking Git-Commit-ID: f8dcd9e81797ae24acc44c84f0eb3b9e6cee9791 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3962 Lines: 102 Commit-ID: f8dcd9e81797ae24acc44c84f0eb3b9e6cee9791 Gitweb: http://git.kernel.org/tip/f8dcd9e81797ae24acc44c84f0eb3b9e6cee9791 Author: Paul Burton AuthorDate: Thu, 20 Apr 2017 10:07:34 +0100 Committer: Thomas Gleixner CommitDate: Thu, 20 Apr 2017 16:07:02 +0200 irqchip/mips-gic: Separate IPI reservation & usage tracking Since commit 2af70a962070 ("irqchip/mips-gic: Add a IPI hierarchy domain") introduced the GIC IPI IRQ domain we have tracked both reservation of interrupts & their use with a single bitmap - ipi_resrv. If an interrupt is reserved for use as an IPI but not actually in use then the appropriate bit is set in ipi_resrv. If an interrupt is either not reserved for use as an IPI or has been allocated as one then the appropriate bit is clear in ipi_resrv. Unfortunately this means that checking whether a bit is set in ipi_resrv to prevent IPI interrupts being allocated for use with a device is broken, because if the interrupt has been allocated as an IPI first then its bit will be clear. Fix this by separating the tracking of IPI reservation & usage, introducing a separate ipi_available bitmap for the latter. This means that ipi_resrv will now always have bits set corresponding to all interrupts reserved for use as IPIs, whether or not they have been allocated yet, and therefore that checking it when allocating device interrupts works as expected. Fixes: 2af70a962070 ("irqchip/mips-gic: Add a IPI hierarchy domain") Signed-off-by: Paul Burton Signed-off-by: Matt Redfearn Cc: linux-mips@linux-mips.org Cc: Jason Cooper Cc: Marc Zyngier Cc: Ralf Baechle Link: http://lkml.kernel.org/r/1492679256-14513-2-git-send-email-matt.redfearn@imgtec.com Signed-off-by: Thomas Gleixner --- drivers/irqchip/irq-mips-gic.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index cd20df1..db058e1 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -55,6 +55,7 @@ static unsigned int gic_cpu_pin; static unsigned int timer_cpu_pin; static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); +DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS); static void __gic_irq_dispatch(void); @@ -746,17 +747,17 @@ static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, return gic_setup_dev_chip(d, virq, spec->hwirq); } else { - base_hwirq = find_first_bit(ipi_resrv, gic_shared_intrs); + base_hwirq = find_first_bit(ipi_available, gic_shared_intrs); if (base_hwirq == gic_shared_intrs) { return -ENOMEM; } /* check that we have enough space */ for (i = base_hwirq; i < nr_irqs; i++) { - if (!test_bit(i, ipi_resrv)) + if (!test_bit(i, ipi_available)) return -EBUSY; } - bitmap_clear(ipi_resrv, base_hwirq, nr_irqs); + bitmap_clear(ipi_available, base_hwirq, nr_irqs); /* map the hwirq for each cpu consecutively */ i = 0; @@ -787,7 +788,7 @@ static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, return 0; error: - bitmap_set(ipi_resrv, base_hwirq, nr_irqs); + bitmap_set(ipi_available, base_hwirq, nr_irqs); return ret; } @@ -802,7 +803,7 @@ void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, return; base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); - bitmap_set(ipi_resrv, base_hwirq, nr_irqs); + bitmap_set(ipi_available, base_hwirq, nr_irqs); } int gic_irq_domain_match(struct irq_domain *d, struct device_node *node, @@ -1098,6 +1099,7 @@ static void __init __gic_init(unsigned long gic_base_addr, 2 * gic_vpes); } + bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS); gic_basic_init(); gic_map_interrupts(node); }