Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031980AbdDTT7W (ORCPT ); Thu, 20 Apr 2017 15:59:22 -0400 Received: from plaes.org ([188.166.43.21]:43502 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030607AbdDTT7U (ORCPT ); Thu, 20 Apr 2017 15:59:20 -0400 Date: Thu, 20 Apr 2017 19:59:17 +0000 From: Priit Laes To: Maxime Ripard Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng , Russell King , Chen-Yu Tsai , Mark Rutland , Rob Herring , Stephen Boyd , Michael Turquette , Philipp Zabel Subject: Re: [linux-sunxi] Re: [PATCH v2 1/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver Message-ID: <20170420195917.GA16113@plaes.org> References: <20170327075438.cw3d6s7zyeemenwr@lukather> <20170404200919.GA22159@plaes.org> <20170407133805.aiythp3hdvuyhcrc@lukather> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170407133805.aiythp3hdvuyhcrc@lukather> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1469 Lines: 53 On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote: > Hi Priit, > > On Tue, Apr 04, 2017 at 08:09:19PM +0000, Priit Laes wrote: > > > > +/* Not documented on A10 */ > > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata", "pll-periph", > > > > + 0x028, BIT(14), 0); > > > > > > The rate doesn't come from pll-periph directly, does it? > > > > So it uses hosc (24MHz parent clock) instead of pll-periph? > > I never looked too much at this, but it looks more like the input is > pll-periph-sata itself. OK, I think I have now fixed most of the issues thanks to Maxime and Chen-Yu and I'm almost ready to send out V3. >From my side there is only single issue remaining - how to create "sata-ext" clock? [snip] static struct ccu_div pll_periph_sata_clk = { .enable = BIT(14), .div = _SUNXI_CCU_DIV(0, 2), .common = { .prediv = 6, .reg = 0x028, .features = CCU_FEATURE_ALL_PREDIV, .hw.init = CLK_HW_INIT("pll-periph-sata", "pll-periph-base", &ccu_nk_ops, 0), }, }; static const char* const sata_parents[] = {"pll-periph-sata", "sata-ext"}; static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents, 0x0c8, 24, 1, BIT(31), 0); [/snip] Should I create a fixed-clock node in the dtsi: sata-ext: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <200000000>; clock-output-names = "sata-ext"; }; And would it also need pio definition? P?ikest, Priit :)