Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1037223AbdDUJ1f (ORCPT ); Fri, 21 Apr 2017 05:27:35 -0400 Received: from foss.arm.com ([217.140.101.70]:34930 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1033889AbdDUJ1d (ORCPT ); Fri, 21 Apr 2017 05:27:33 -0400 Date: Fri, 21 Apr 2017 10:27:06 +0100 From: Mark Rutland To: Haiying Wang Cc: linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, roy.pledge@nxp.com, stuyoder@gmail.com Subject: Re: [PATCH 3/3] bus: fsl-mc: dpio: change CENA regs to be cacheable Message-ID: <20170421092706.GC6406@leverpostej> References: <1492716858-24509-1-git-send-email-Haiying.Wang@nxp.com> <1492716858-24509-4-git-send-email-Haiying.Wang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1492716858-24509-4-git-send-email-Haiying.Wang@nxp.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1967 Lines: 50 On Thu, Apr 20, 2017 at 03:34:18PM -0400, Haiying Wang wrote: > plus non-shareable to meet the performance requirement. > QMan's CENA region contains registers and structures that > are 64byte in size and are inteneded to be accessed using a > single 64 byte bus transaction, therefore this portal > memory should be configured as cache-enabled. Also because > the write allocate stash transcations of QBMan should be > issued as cachable and non-coherent(non-sharable), we > need to configure this region to be non-shareable. > > Signed-off-by: Haiying Wang > --- > drivers/staging/fsl-mc/bus/dpio/dpio-driver.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c > index e36da20..97f909c 100644 > --- a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c > +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c > @@ -168,10 +168,10 @@ static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev) > desc.cpu = next_cpu; > > /* > - * Set the CENA regs to be the cache inhibited area of the portal to > - * avoid coherency issues if a user migrates to another core. > + * Set the CENA regs to be the cache enalbed area of the portal to > + * archieve the best performance. Is migrating to another core no longer a concern? As with my prior comments regarding the Non-Shareable mapping, I do not thing this makes sense. Thanks, Mark. > */ > - desc.regs_cena = ioremap_wc(dpio_dev->regions[1].start, > + desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[1].start, > resource_size(&dpio_dev->regions[1])); > desc.regs_cinh = ioremap(dpio_dev->regions[1].start, > resource_size(&dpio_dev->regions[1])); > -- > 2.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel