Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1427870AbdDWIUz (ORCPT ); Sun, 23 Apr 2017 04:20:55 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:54282 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1427903AbdDWIRn (ORCPT ); Sun, 23 Apr 2017 04:17:43 -0400 From: Ryder Lee To: Kishon Vijay Abraham I , Rob Herring CC: Matthias Brugger , , , , , Ryder Lee Subject: [PATCH 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY Date: Sun, 23 Apr 2017 16:17:33 +0800 Message-ID: <1492935453-17373-3-git-send-email-ryder.lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492935453-17373-1-git-send-email-ryder.lee@mediatek.com> References: <1492935453-17373-1-git-send-email-ryder.lee@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2214 Lines: 83 Add documentation for PCIe PHY available in MT7623 series SoCs. Signed-off-by: Ryder Lee --- .../devicetree/bindings/phy/phy-mt7623-pcie.txt | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt diff --git a/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt b/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt new file mode 100644 index 0000000..27a9253 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt @@ -0,0 +1,67 @@ +Mediatek MT7623 PCIe PHY +----------------------- + +Required properties: + - compatible: Should contain "mediatek,mt7623-pcie-phy" + - #phy-cells: must be 0 + - clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must be "refclk" + - resets: Must contain an entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must be "phy" + +Optional properties: + - phy-switch: The PHY on PCIe port2 is shared with USB u3phy2. If you + want to enable port2, you should contain it. + +Example: + + pcie0_phy: pciephy@1a149000 { + compatible = "mediatek,mt7623-pcie-phy"; + reg = <0 0x1a149000 0 0x1000>; + clocks = <&clk26m>; + clock-names = "pciephya_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie1_phy: pciephy@1a14a000 { + compatible = "mediatek,mt7623-pcie-phy"; + reg = <0 0x1a14a000 0 0x1000>; + clocks = <&clk26m>; + clock-names = "pciephya_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie2_phy: pciephy@1a244000 { + compatible = "mediatek,mt7623-pcie-phy"; + reg = <0 0x1a244000 0 0x1000>; + clocks = <&clk26m>; + clock-names = "pciephya_ref"; + #phy-cells = <0>; + + phy-switch = <&hifsys>; + status = "disabled"; + }; + +Specifying phy control of devices +--------------------------------- + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy node and phy-names. + +Example: + +#include + +pcie: pcie@1a140000 { + ... + pcie@1,0 { + ... + phys = <&pcie0_phy>; + phy-names = "pcie-phy0"; + } + ... +}; -- 1.9.1