Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1167768AbdDXJPC (ORCPT ); Mon, 24 Apr 2017 05:15:02 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:5386 "EHLO dggrg02-dlp.huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1167748AbdDXJOu (ORCPT ); Mon, 24 Apr 2017 05:14:50 -0400 Subject: Re: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled To: Marc Zyngier , "Lixiaoping (Timmy)" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" References: <20170404171826.25030-1-marc.zyngier@arm.com> <20170404171826.25030-16-marc.zyngier@arm.com> <58FDB05B.6020108@huawei.com> <95ac3477-436a-22ad-80f4-d4bed6c73e1c@arm.com> <493e2b26-96a2-4b92-fd4b-f6f7d5c89fb5@arm.com> CC: Mark Rutland , Catalin Marinas , Daniel Lezcano , "Will Deacon" , Scott Wood , Hanjun Guo , Dingtianhong , dann frazier , Thomas Gleixner From: Hanjun Guo Message-ID: <58FDC1F5.3000401@huawei.com> Date: Mon, 24 Apr 2017 17:14:29 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <493e2b26-96a2-4b92-fd4b-f6f7d5c89fb5@arm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.17.188] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.58FDC205.019D,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 36672843975fab3edbf95890322bed8e Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1685 Lines: 47 On 2017/4/24 16:40, Marc Zyngier wrote: > On 24/04/17 09:25, Lixiaoping (Timmy) wrote: >> Hi Marc, >> >> Sorry about previous email's confidential info. Please forget it. >> >> +#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 14, 0, 0) | \ >> + ESR_ELx_SYS64_ISS_DIR_READ) >> >> I think (3, 3, 14, 0, 0) should be (3, 3, 0, 14, 0)? > Thanks for spotting this. I assumed that the sys_reg() and > SR_ELx_SYS64_ISS_SYS_VAL() macros took their arguments in the same > order. That would have been too easy... ;-) > > Amended patch below, please let me know if it works for you. > > Thanks, > > M. > > >From 4444c86a97c1a487e12c319fdc197c88631d72b5 Mon Sep 17 00:00:00 2001 > From: Marc Zyngier > Date: Mon, 24 Apr 2017 09:04:03 +0100 > Subject: [PATCH] arm64: Add CNTFRQ_EL0 trap handler > > We now trap accesses to CNTVCT_EL0 when the counter is broken > enough to require the kernel to mediate the access. But it > turns out that some existing userspace (such as OpenMPI) do > probe for the counter frequency, leading to an UNDEF exception > as CNTVCT_EL0 and CNTFRQ_EL0 share the same control bit. > > The fix is to handle the exception the same way we do for CNTVCT_EL0. > > Fixes: a86bd139f2ae ("arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled") > Reported-by: Hanjun Guo > Signed-off-by: Marc Zyngier > --- I tested this patch and the undefined instruction error is gone, I can get the FREQ in the user space now, thank you very much for the quick response. Tested-by: Hanjun Guo Reviewed-by: Hanjun Guo Thanks Hanjun