Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1170839AbdDXNP1 (ORCPT ); Mon, 24 Apr 2017 09:15:27 -0400 Received: from mail-io0-f181.google.com ([209.85.223.181]:36727 "EHLO mail-io0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1170716AbdDXNPU (ORCPT ); Mon, 24 Apr 2017 09:15:20 -0400 MIME-Version: 1.0 In-Reply-To: <197e6ca51bb83ae865022d7ffd085d06dfee7795.1492190203.git.sathyanarayanan.kuppuswamy@linux.intel.com> References: <197e6ca51bb83ae865022d7ffd085d06dfee7795.1492190203.git.sathyanarayanan.kuppuswamy@linux.intel.com> From: Linus Walleij Date: Mon, 24 Apr 2017 15:15:18 +0200 Message-ID: Subject: Re: [PATCH v1 2/2] gpio: gpio-wcove: fix irq pending status bit width To: Kuppuswamy Sathyanarayanan Cc: Alexandre Courbot , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , sathyaosid@gmail.com, Mika Westerberg , Andy Shevchenko Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 702 Lines: 20 On Fri, Apr 14, 2017 at 7:29 PM, wrote: > From: Kuppuswamy Sathyanarayanan > > Whiskey cove PMIC has three GPIO banks with total number of 13 GPIO > pins. But when checking for the pending status, for_each_set_bit() uses > bit width of 7 and hence it only checks the status for first 7 GPIO pins > missing to check/clear the status of rest of the GPIO pins. This patch > fixes this issue. > > Signed-off-by: Kuppuswamy Sathyanarayanan Looks reasonable so patch applied. Just looping in Mika & Andy so they have an idea about what's going on. Yours, Linus Walleij