Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1430114AbdDYLMH (ORCPT ); Tue, 25 Apr 2017 07:12:07 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5930 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1429042AbdDYLL4 (ORCPT ); Tue, 25 Apr 2017 07:11:56 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 25 Apr 2017 04:11:55 -0700 Subject: Re: [PATCH V3 4/4] soc/tegra: pmc: Use the new reset APIs to manage reset controllers To: Vivek Gautam References: <1492514488-27385-1-git-send-email-vivek.gautam@codeaurora.org> <1492514488-27385-5-git-send-email-vivek.gautam@codeaurora.org> <1493116400.2394.32.camel@pengutronix.de> <5e0c2030-ad96-15fc-1dc4-db6cd11d52c3@codeaurora.org> CC: Philipp Zabel , , , , , , , , , Thierry Reding From: Jon Hunter Message-ID: Date: Tue, 25 Apr 2017 12:11:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <5e0c2030-ad96-15fc-1dc4-db6cd11d52c3@codeaurora.org> X-Originating-IP: [10.21.132.162] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2265 Lines: 56 On 25/04/17 12:06, Vivek Gautam wrote: > On 04/25/2017 04:24 PM, Jon Hunter wrote: >> On 25/04/17 11:33, Philipp Zabel wrote: >>> On Tue, 2017-04-25 at 11:05 +0100, Jon Hunter wrote: >>>> On 25/04/17 05:15, Vivek Gautam wrote: >>>>> On 04/24/2017 06:15 PM, Jon Hunter wrote: >>>>>> On 18/04/17 12:21, Vivek Gautam wrote: >>>>>>> Make use of reset_control_array_*() set of APIs to manage >>>>>>> an array of reset controllers available with the device. >>>>>> Before we apply this patch, I need to check to see if the order of >>>>>> the >>>>>> resets managed by the PMC driver matter. Today the order of the >>>>>> resets >>>>>> is determined by the order they appear in the DT node and although >>>>>> the >>>>>> new APIs work in the same way they do not guarantee this. So let me >>>>>> check to see if we can any concerns about ordering here. Otherwise >>>>>> would >>>>>> be nice to use these APIs. >>>>> Right, that will be perfect. >>>> So I don't see any restrictions here and so I think this change is >>>> fine. >>> Thank you for checking. >>> >>>> BTW, for the DT case, is there any reason why we don't just say the >>>> order will be determine by the order the resets are list in the DT >>>> node? >>> I'd rather not make any promises, so I don't have to care about keeping >>> them. This makes it easier to think about and allows for more freedom in >>> changing the core code if needed. >>> >>> What if in the future there is a use case for enabling a bunch of resets >>> by flipping a number of bits in a single register at the same time? Or >>> if people accidentally depend on the ordering when in reality there is a >>> small delay necessary between assertions that just happens to be hidden >>> by the framework overhead? >>> >>> If there is a use case for an array of reset controls that must be >>> (de)asserted in a fixed order and doesn't need any delay between the >>> steps and is not suitable to be described by named resets for some >>> reason, we can discuss this. Until then, I'm happy that tegra pmc can >>> handle arrays without any particular ordering. >> OK, makes sense. > > Thanks Jon for testing this. Not tested yet :-) However, I will test this just to confirm. Are you planning on sending out a v4 soon? Jon -- nvpublic