Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1951508AbdDYQUS (ORCPT ); Tue, 25 Apr 2017 12:20:18 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:34482 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1951492AbdDYQUJ (ORCPT ); Tue, 25 Apr 2017 12:20:09 -0400 From: "Jingoo Han" To: "'Jon Masters'" , "'Lorenzo Pieralisi'" , Cc: , , "'Pratyush Anand'" , "'Arnd Bergmann'" , "'Jonathan Corbet'" , "'Will Deacon'" , "'Bjorn Helgaas'" , "'Mingkai Hu'" , "'Tanmay Inamdar'" , "'Murali Karicheri'" , "'Russell King'" , "'Bharat Kumar Gogada'" , "'Ray Jui'" , "'Wenrui Li'" , "'Shawn Lin'" , "'Minghuan Lian'" , "'Catalin Marinas'" , "'Jon Mason'" , "'Gabriele Paoloni'" , "'Thomas Petazzoni'" , "'Joao Pinto'" , "'Thierry Reding'" , "'Luis R . Rodriguez'" , "'Michal Simek'" , "'Stanimir Varbanov'" , "'Zhou Wang'" , "'Roy Zang'" , "'Benjamin Herrenschmidt'" , "'John Garry'" References: <20170419164913.19674-1-lorenzo.pieralisi@arm.com> <2e24e205-d761-9172-9463-4a53e1a0de4d@jonmasters.org> In-Reply-To: <2e24e205-d761-9172-9463-4a53e1a0de4d@jonmasters.org> Subject: Re: [PATCH v4 00/21] PCI: fix config space memory mappings Date: Tue, 25 Apr 2017 12:20:02 -0400 Message-ID: <000101d2bddf$cd442e80$67cc8b80$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQMEXGkO3eUKaJOMePDUqvXZRiCR0wFaI1eGn2g1KaA= Content-Language: ko Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 967 Lines: 25 On Tuesday, April 25, 2017 2:41 AM, Jon Masters wrote: > > On 04/19/2017 12:48 PM, Lorenzo Pieralisi wrote: > > > On some platforms (ie ARM/ARM64) ioremap fails to comply with the PCI > > configuration non-posted write transactions requirement, because it > > provides a memory mapping that issues "bufferable" or, in PCI terms > > "posted" write transactions. Likewise, the current pci_remap_iospace() > > implementation maps the physical address range that the PCI translates > > to I/O space cycles to virtual address space through pgprot_device() > > attributes that on eg ARM64 provides a memory mapping issuing > > posted writes transactions, which is not PCI specifications compliant. > > Side note that I've pinged all of the ARM server vendors and asked them > to verify this patch series on their platforms. Good! I really want to know the result of these patches on ARM serves. Please share it with us. Good luck. Best regards, Jingoo Han > > Jon.