Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1432534AbdDYRuT (ORCPT ); Tue, 25 Apr 2017 13:50:19 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59980 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1432514AbdDYRuL (ORCPT ); Tue, 25 Apr 2017 13:50:11 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E72FF61475 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org MIME-Version: 1.0 In-Reply-To: References: <1492514488-27385-1-git-send-email-vivek.gautam@codeaurora.org> <1492514488-27385-5-git-send-email-vivek.gautam@codeaurora.org> <1493116400.2394.32.camel@pengutronix.de> <5e0c2030-ad96-15fc-1dc4-db6cd11d52c3@codeaurora.org> From: Vivek Gautam Date: Tue, 25 Apr 2017 23:20:08 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V3 4/4] soc/tegra: pmc: Use the new reset APIs to manage reset controllers To: Jon Hunter Cc: Philipp Zabel , Stephen Warren , Felipe Balbi , "linux-kernel@vger.kernel.org" , linux-tegra , Linux USB Mailing List , "thierry.reding" , Greg KH , linux-arm-msm@vger.kernel.org, Thierry Reding Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2541 Lines: 62 On Tue, Apr 25, 2017 at 4:41 PM, Jon Hunter wrote: > > On 25/04/17 12:06, Vivek Gautam wrote: >> On 04/25/2017 04:24 PM, Jon Hunter wrote: >>> On 25/04/17 11:33, Philipp Zabel wrote: >>>> On Tue, 2017-04-25 at 11:05 +0100, Jon Hunter wrote: >>>>> On 25/04/17 05:15, Vivek Gautam wrote: >>>>>> On 04/24/2017 06:15 PM, Jon Hunter wrote: >>>>>>> On 18/04/17 12:21, Vivek Gautam wrote: >>>>>>>> Make use of reset_control_array_*() set of APIs to manage >>>>>>>> an array of reset controllers available with the device. >>>>>>> Before we apply this patch, I need to check to see if the order of >>>>>>> the >>>>>>> resets managed by the PMC driver matter. Today the order of the >>>>>>> resets >>>>>>> is determined by the order they appear in the DT node and although >>>>>>> the >>>>>>> new APIs work in the same way they do not guarantee this. So let me >>>>>>> check to see if we can any concerns about ordering here. Otherwise >>>>>>> would >>>>>>> be nice to use these APIs. >>>>>> Right, that will be perfect. >>>>> So I don't see any restrictions here and so I think this change is >>>>> fine. >>>> Thank you for checking. >>>> >>>>> BTW, for the DT case, is there any reason why we don't just say the >>>>> order will be determine by the order the resets are list in the DT >>>>> node? >>>> I'd rather not make any promises, so I don't have to care about keeping >>>> them. This makes it easier to think about and allows for more freedom in >>>> changing the core code if needed. >>>> >>>> What if in the future there is a use case for enabling a bunch of resets >>>> by flipping a number of bits in a single register at the same time? Or >>>> if people accidentally depend on the ordering when in reality there is a >>>> small delay necessary between assertions that just happens to be hidden >>>> by the framework overhead? >>>> >>>> If there is a use case for an array of reset controls that must be >>>> (de)asserted in a fixed order and doesn't need any delay between the >>>> steps and is not suitable to be described by named resets for some >>>> reason, we can discuss this. Until then, I'm happy that tegra pmc can >>>> handle arrays without any particular ordering. >>> OK, makes sense. >> >> Thanks Jon for testing this. > > Not tested yet :-) > > However, I will test this just to confirm. Are you planning on sending > out a v4 soon? Yes, I will send a v4 soon this week. Thanks Vivek -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project