Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1956445AbdDZJdK (ORCPT ); Wed, 26 Apr 2017 05:33:10 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54671 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2997098AbdDZJ0i (ORCPT ); Wed, 26 Apr 2017 05:26:38 -0400 From: To: , , , , , , , CC: , , , Sean Wang Subject: [PATCH v2 10/30] arm: dts: mt7623: add spi nodes to the mt7623.dtsi file Date: Wed, 26 Apr 2017 17:25:54 +0800 Message-ID: <1493198774-4478-11-git-send-email-sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com> References: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1904 Lines: 65 From: Sean Wang Add spi controller nodes to the mt7623.dtsi file Signed-off-by: John Crispin Signed-off-by: Sean Wang --- arch/arm/boot/dts/mt7623.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index adb4793..131808c 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -288,6 +288,48 @@ status = "disabled"; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI0_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11016000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11016000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI1_SEL>, + <&pericfg CLK_PERI_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11017000 { + compatible = "mediatek,mt7623-spi", + "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11017000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI2_SEL>, + <&pericfg CLK_PERI_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", -- 1.9.1