Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S3001220AbdDZOa5 (ORCPT ); Wed, 26 Apr 2017 10:30:57 -0400 Received: from mga01.intel.com ([192.55.52.88]:39726 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S3001205AbdDZOat (ORCPT ); Wed, 26 Apr 2017 10:30:49 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,254,1488873600"; d="scan'208";a="1161230045" Date: Wed, 26 Apr 2017 17:30:40 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Michel =?iso-8859-1?Q?D=E4nzer?= Cc: Daniel Vetter , dri-devel@lists.freedesktop.org, Gerd Hoffmann , amd-gfx@lists.freedesktop.org, open list Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format Message-ID: <20170426143040.GW30290@intel.com> References: <20170424062532.26722-1-kraxel@redhat.com> <20170424062532.26722-4-kraxel@redhat.com> <3b872a56-80b5-0c44-712f-a9517489eb24@daenzer.net> <20170425095259.GK30290@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 859 Lines: 27 On Wed, Apr 26, 2017 at 11:00:09AM +0900, Michel D?nzer wrote: > On 25/04/17 06:52 PM, Ville Syrj?l? wrote: > > On Tue, Apr 25, 2017 at 12:18:52PM +0900, Michel D?nzer wrote: > >> On 24/04/17 03:25 PM, Gerd Hoffmann wrote: > >>> +#ifdef __BIG_ENDIAN > >>> + switch (bpp) { > >>> + case 8: > >>> + fmt = DRM_FORMAT_C8; > >>> + break; > >>> + case 24: > >>> + fmt = DRM_FORMAT_BGR888; > >>> + break; > >> > >> BTW, endianness as a concept cannot apply to 8 or 24 bpp formats. > > > > To 8bpp no, but it can easily apply to 24bpp. > > Any byte swapping rips apart the bytes of a 24bpp pixel, so those > formats only make sense as straight array formats. In my book little endian just means "lsb is stored in the lowest memory address". The fact that your CPU/GPU can't do 3 byte swaps is not relevant for that definition IMO. -- Ville Syrj?l? Intel OTC