From: "Jingoo Han" <jingoohan1@gmail.com>
To: "'Dongdong Liu'" <liudongdong3@huawei.com>,
        "'Khuong Dinh'" <kdinh@apm.com>, "'Jon Masters'" <jcm@jonmasters.org>,
        "'Lorenzo Pieralisi'" <lorenzo.pieralisi@arm.com>,
        <linux-pci@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
        "'Pratyush Anand'" <pratyush.anand@gmail.com>,
        "'Arnd Bergmann'" <arnd@arndb.de>,
        "'Jonathan Corbet'" <corbet@lwn.net>,
        "'Will Deacon'" <will.deacon@arm.com>,
        "'Bjorn Helgaas'" <bhelgaas@google.com>,
        "'Mingkai Hu'" <mingkai.hu@freescale.com>,
        "'Tanmay Inamdar'" <tinamdar@apm.com>,
        "'Murali Karicheri'" <m-karicheri2@ti.com>,
        "'Russell King'" <linux@armlinux.org.uk>,
        "'Bharat Kumar Gogada'" <bharat.kumar.gogada@xilinx.com>,
        "'Ray Jui'" <rjui@broadcom.com>,
        "'Wenrui Li'" <wenrui.li@rock-chips.com>,
        "'Shawn Lin'" <shawn.lin@rock-chips.com>,
        "'Minghuan Lian'" <minghuan.Lian@freescale.com>,
        "'Catalin Marinas'" <catalin.marinas@arm.com>,
        "'Jon Mason'" <jonmason@broadcom.com>,
        "'Gabriele Paoloni'" <gabriele.paoloni@huawei.com>,
        "'Thomas Petazzoni'" <thomas.petazzoni@free-electrons.com>,
        "'Joao Pinto'" <Joao.Pinto@synopsys.com>,
        "'Thierry Reding'" <thierry.reding@gmail.com>,
        "'Luis R . Rodriguez'" <mcgrof@kernel.org>,
        "'Michal Simek'" <michal.simek@xilinx.com>,
        "'Stanimir Varbanov'" <svarbanov@mm-sol.com>,
        "'Zhou Wang'" <wangzhou1@hisilicon.com>,
        "'Roy Zang'" <tie-fei.zang@freescale.com>,
        "'Benjamin Herrenschmidt'" <benh@kernel.crashing.org>,
        "'John Garry'" <john.garry@huawei.com>,
        "'Linuxarm'" <linuxarm@huawei.com>
References: <20170419164913.19674-1-lorenzo.pieralisi@arm.com> <2e24e205-d761-9172-9463-4a53e1a0de4d@jonmasters.org> <361fde15-5ba3-d33b-f946-003e89ba071f@huawei.com>
In-Reply-To: <361fde15-5ba3-d33b-f946-003e89ba071f@huawei.com>
Subject: Re: [PATCH v4 00/21] PCI: fix config space memory mappings
Date: Wed, 26 Apr 2017 13:24:48 -0400
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On Wednesday, April 26, 2017 6:54 AM, Dongdong Liu wrote;
> 
> Tested-by: Dongdong Liu <liudongdong3@huawei.com>
> 
> I tested the patchset on HiSilicon ARM64 D05 board.It works ok with 82599
> netcard.

Thank you for testing these patches. HiSilicon PCIe may use Designware-based
PCIe controller. In my opinion, other Designware-based PCIe controller will
work properly.

To Dongdong Liu, Khuong Dinh, and other people,
If possible, can you check the output of 'lspci -v'?
If you find something different, please share it with us.
Good luck.

Best regards,
Jingoo Han

> 
> Thanks,
> Dongdong
> 在 2017/4/25 14:40, Jon Masters 写道:
> > On 04/19/2017 12:48 PM, Lorenzo Pieralisi wrote:
> >
> >> On some platforms (ie ARM/ARM64) ioremap fails to comply with the PCI
> >> configuration non-posted write transactions requirement, because it
> >> provides a memory mapping that issues "bufferable" or, in PCI terms
> >> "posted" write transactions. Likewise, the current pci_remap_iospace()
> >> implementation maps the physical address range that the PCI translates
> >> to I/O space cycles to virtual address space through pgprot_device()
> >> attributes that on eg ARM64 provides a memory mapping issuing
> >> posted writes transactions, which is not PCI specifications compliant.
> >
> > Side note that I've pinged all of the ARM server vendors and asked them
> > to verify this patch series on their platforms.
> >
> > Jon.
> >
> > .
> >