Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1162522AbdD0Njm (ORCPT ); Thu, 27 Apr 2017 09:39:42 -0400 Received: from mail-by2nam01on0053.outbound.protection.outlook.com ([104.47.34.53]:31072 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751194AbdD0Nj0 (ORCPT ); Thu, 27 Apr 2017 09:39:26 -0400 Authentication-Results: caviumnetworks.com; dkim=none (message not signed) header.d=none;caviumnetworks.com; dmarc=none action=none header.from=cavium.com; Date: Thu, 27 Apr 2017 15:39:10 +0200 From: Robert Richter To: Geetha sowjanya Cc: will.deacon@arm.com, robin.murphy@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, iommu@lists.linux-foundation.org, jcm@redhat.com, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com, linu.cherian@cavium.com, Geetha Subject: Re: [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Message-ID: <20170427133910.GB31368@rric.localdomain> References: <1493293584-20287-1-git-send-email-gakula@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; 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Errata ID #74 > SMMU register alias Page 1 is not implemented > 2. Errata ID #126 > SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync > > The following patchset does software workaround for these two erratas. > > This series is based on RFC patch. > https://www.spinics.net/lists/arm-kernel/msg575739.html > > As suggested by Will Deacon, code is modified to use silicon id to > enable errata#74 workaround. Can we go with the previous series [1] and: * drop the iort model numbering part, * add an enablement function that enables flags (smmu->options) depending on midr values (which replaces the macro code)? E.g.: static void acpi_smmu_enable_cavium(struct arm_smmu_device *smmu) { u32 cpu_model; if (!IS_ENABLED(CONFIG_ARM64)) return; cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK; switch (cpu_model) { case ...: case ...: break; default: /* No Cavium CN99xx SMMU v3 */ return; } smmu->options |= (ARM_SMMU_OPT_PAGE0_REGS_ONLY | ARM_SMMU_OPT_USE_SHARED_IRQS); } -Robert [1] [RFC PATCH 0/7] Cavium CN99xx SMMUv3 Errata workarounds https://marc.info/?l=linux-acpi&m=149192179623708&w=2 > > Linu Cherian (1): > iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 > > Geetha (2): > arm64: Add MIDR values for Cavium cn99xx SoCs > iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 > > Documentation/arm64/silicon-errata.txt | 2 ++ > arch/arm64/include/asm/cputype.h | 3 ++ > drivers/acpi/arm64/iort.c | 14 +++++++- > drivers/iommu/arm-smmu-v3.c | 64 +++++++++++++++++++++++++++++----- > 4 files changed, 73 insertions(+), 10 deletions(-) > > -- > 1.9.1 >