Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S939448AbdD0QnX (ORCPT ); Thu, 27 Apr 2017 12:43:23 -0400 Received: from foss.arm.com ([217.140.101.70]:39596 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755653AbdD0QnP (ORCPT ); Thu, 27 Apr 2017 12:43:15 -0400 Date: Thu, 27 Apr 2017 17:42:37 +0100 From: Mark Rutland To: Geetha sowjanya Cc: will.deacon@arm.com, robin.murphy@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, iommu@lists.linux-foundation.org, jcm@redhat.com, linu.cherian@cavium.com, linux-kernel@vger.kernel.org, geethasowjanya.akula@gmail.com, linux-acpi@vger.kernel.org, robert.richter@cavium.com, catalin.marinas@arm.com, Geetha , sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Message-ID: <20170427164237.GA7114@leverpostej> References: <1493293584-20287-1-git-send-email-gakula@caviumnetworks.com> <1493293584-20287-3-git-send-email-gakula@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1493293584-20287-3-git-send-email-gakula@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 572 Lines: 18 On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote: > + /* > + * Override the size, for Cavium CN99xx implementations > + * which doesn't support the page 1 SMMU register space. > + */ > + cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK; > + if (cpu_model == MIDR_THUNDERX_99XX || > + cpu_model == MIDR_BRCM_VULCAN) > + size = SZ_64K; If you're trying to identify an SMMU erratum, identify the SMMU, not the CPU it happens to be paired with this time. There are ID registers in the SMMU you can use to do so. NAK to using the CPU ID here. Mark.