Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1163625AbdD0RBo (ORCPT ); Thu, 27 Apr 2017 13:01:44 -0400 Received: from foss.arm.com ([217.140.101.70]:39796 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1163196AbdD0RAc (ORCPT ); Thu, 27 Apr 2017 13:00:32 -0400 Date: Thu, 27 Apr 2017 18:00:31 +0100 From: Will Deacon To: Mark Rutland Cc: Geetha sowjanya , robin.murphy@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, iommu@lists.linux-foundation.org, jcm@redhat.com, linu.cherian@cavium.com, linux-kernel@vger.kernel.org, geethasowjanya.akula@gmail.com, linux-acpi@vger.kernel.org, robert.richter@cavium.com, catalin.marinas@arm.com, Geetha , sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Message-ID: <20170427170030.GF1890@arm.com> References: <1493293584-20287-1-git-send-email-gakula@caviumnetworks.com> <1493293584-20287-3-git-send-email-gakula@caviumnetworks.com> <20170427164237.GA7114@leverpostej> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170427164237.GA7114@leverpostej> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 802 Lines: 22 On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote: > On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote: > > + /* > > + * Override the size, for Cavium CN99xx implementations > > + * which doesn't support the page 1 SMMU register space. > > + */ > > + cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK; > > + if (cpu_model == MIDR_THUNDERX_99XX || > > + cpu_model == MIDR_BRCM_VULCAN) > > + size = SZ_64K; > > If you're trying to identify an SMMU erratum, identify the SMMU, not the > CPU it happens to be paired with this time. > > There are ID registers in the SMMU you can use to do so. > > NAK to using the CPU ID here. Agreed. I had some off-list discussion with Geetha where we agreed to use the "silicon ID", which I assumed was the SMMU IIDR register. Will