Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756620AbdD1MPy (ORCPT ); Fri, 28 Apr 2017 08:15:54 -0400 Received: from mail-qk0-f169.google.com ([209.85.220.169]:35664 "EHLO mail-qk0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754113AbdD1MPf (ORCPT ); Fri, 28 Apr 2017 08:15:35 -0400 MIME-Version: 1.0 In-Reply-To: References: <1493281194-5200-1-git-send-email-jacopo+renesas@jmondi.org> <1493281194-5200-2-git-send-email-jacopo+renesas@jmondi.org> From: Andy Shevchenko Date: Fri, 28 Apr 2017 15:15:33 +0300 Message-ID: Subject: Re: [PATCH v5 01/10] pinctrl: generic: Add bi-directional and output-enable To: Chris Brandt Cc: Linus Walleij , Jacopo Mondi , Geert Uytterhoeven , Laurent Pinchart , Rob Herring , Mark Rutland , Russell King - ARM Linux , Linux-Renesas , "linux-gpio@vger.kernel.org" , devicetree , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v3SCHFxL023009 Content-Length: 1478 Lines: 28 On Fri, Apr 28, 2017 at 3:07 PM, Chris Brandt wrote: > On Friday, April 28, 2017, Linus Walleij wrote: >> > For me it looks like you are trying to alias open-drain + bias or >> > alike. Don't actually see the benefit of it. >> >> Andy is bringing up a valid point. And I remember asking about this before. >> >> What does "bi-directional" really mean, electrically speaking? > Take the SDHI data pins. You send AND receive data over those pins (and they are not open drain). Can you point to schematics and electrical characteristics of such buffer? (Yes, I can imagine one case where it's possible to have an "automatic" switch based on which current is bigger output of your side or remote's. But! I would like to see actual specifications to prove this or otherwise.) > The issue is that the PFC HW that enables the connections between the SDHI IP block and the I/O pad buffers can only enable one path/signal/direction to the buffer enables (in or out). So for a pin that needs both directions, the PFC enables output and the "bidirectional register" is used to enable the input buffer as well. > In the RZ/A1 HW manual you can kind of see that in 54.18 Port Control Logical Diagram (but that wasn't obvious to me at first). Please, post a link to it or copy essential parts. I'm quite skeptical that cheap hardware can implement something more costable than simplest open-source / open-drain + bias. -- With Best Regards, Andy Shevchenko