Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756687AbdD1O5H (ORCPT ); Fri, 28 Apr 2017 10:57:07 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:57203 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751237AbdD1O5A (ORCPT ); Fri, 28 Apr 2017 10:57:00 -0400 Subject: Re: [PATCH] clk: stm32h7: Add stm32h743 clock driver To: Stephen Boyd References: <1489569810-24350-1-git-send-email-gabriel.fernandez@st.com> <20170405223233.GJ7065@codeaurora.org> <20170407195152.GH7065@codeaurora.org> CC: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Nicolas Pitre , Arnd Bergmann , , , , Lee Jones , , , , , , , From: Gabriel Fernandez Message-ID: <7a8082a9-e62c-0120-e680-bef63eb892ae@st.com> Date: Fri, 28 Apr 2017 16:56:16 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20170407195152.GH7065@codeaurora.org> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG4NODE3.st.com (10.75.127.12) To SFHDAG4NODE2.st.com (10.75.127.11) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-04-28_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2049 Lines: 63 Hi Stephen Sorry for delay i was on sick live On 04/07/2017 09:51 PM, Stephen Boyd wrote: > On 04/06, Gabriel Fernandez wrote: >> On 04/06/2017 12:32 AM, Stephen Boyd wrote: >>> On 03/15, gabriel.fernandez@st.com wrote: >>>> diff --git a/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt >>>> new file mode 100644 >>>> index 0000000..9d4b587 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt >>>> @@ -0,0 +1,152 @@ >>>> + >>>> + rcc: rcc@58024400 { >>>> + #reset-cells = <1>; >>>> + #clock-cells = <2> >>>> + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; >>>> + reg = <0x58024400 0x400>; >>>> + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>; >>>> + >>>> + st,syscfg = <&pwrcfg>; >>>> + >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + >>>> + vco1@58024430 { >>>> + #clock-cells = <0>; >>>> + compatible = "stm32,pll"; >>>> + reg = <0>; >>> reg is super confusing and doesn't match unit address. >> ok i fixed it in the v2 >> >>>> + }; >>> Why? Shouldn't we know this from the compatible string how many >>> PLLs there are and where they're located? Export the PLLs through >>> rcc node's clock-cells? >>> >> Because i need to offer the possibility to change the PLL VCO >> frequencies at the start-up of this driver clock. >> The VCO algorithm needs a division factor, a multiplication factor >> and a fractional factor. >> Lot's of solution are possible for one frequency and it's nightmare >> to satisfy the 3 output dividers of the PLL. > Sure, but do we need to configure that on a per-board basis or a > per-SoC basis? If it's just some configuration, I wonder why we > don't put that into the driver and base it off some compatible > string that includes the SoC the device is for. > I prefer to let in first, the responsibility of the boot loader to change VCO parameters. Then i propose a new version without DT configuration of PLL's are you ok for that ? best regards Gabriel To simply