Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1426660AbdD1VJb (ORCPT ); Fri, 28 Apr 2017 17:09:31 -0400 Received: from mail-io0-f194.google.com ([209.85.223.194]:33099 "EHLO mail-io0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1163425AbdD1VJ0 (ORCPT ); Fri, 28 Apr 2017 17:09:26 -0400 Date: Fri, 28 Apr 2017 16:09:24 -0500 From: Rob Herring To: Ryder Lee Cc: Bjorn Helgaas , Arnd Bergmann , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Red Hung Subject: Re: [PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe Message-ID: <20170428210924.y6xdv4trqbmyn5me@rob-hp-laptop> References: <1493370634-7038-1-git-send-email-ryder.lee@mediatek.com> <1493370634-7038-3-git-send-email-ryder.lee@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1493370634-7038-3-git-send-email-ryder.lee@mediatek.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 8237 Lines: 207 On Fri, Apr 28, 2017 at 05:10:34PM +0800, Ryder Lee wrote: > Add binding document for Mediatek PCIe Gen2 v1 host controller driver. > > Signed-off-by: Ryder Lee > --- > .../bindings/pci/mediatek,gen2v1-pcie.txt | 174 +++++++++++++++++++++ > 1 file changed, 174 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt > > diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt > new file mode 100644 > index 0000000..545d8cf > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt > @@ -0,0 +1,174 @@ > +Mediatek Gen2 V1 PCIe controller > + > +PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root > +ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3 > +PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for > +data access and 1 bus slave for Configuration and Status Register access. > + > +This controller is available on MT7623 series SoCs. > + > +Required properties: > +- compatible: Should contain "mediatek,gen2v1-pcie". > +- device_type: Must be "pci" > +- reg: Base addresses and lengths of the PCIe controller. > +- #address-cells: Address representation for root ports (must be 3) > + - cell 0 specifies the bus and device numbers of the root port: > + [23:16]: bus number > + [15:11]: device number > + - cell 1 denotes the upper 32 address bits and should be 0 > + - cell 2 contains the lower 32 address bits and is used to translate to the > + CPU address space This is all standard PCI bus binding. You don't need to define it here. "must be 3" is sufficient. > +- #size-cells: Size representation for root ports (must be 2) > +- #interrupt-cells: Size representation for interrupts (must be 1) > +- interrupts: Three interrupt outputs of the controller. Must contain an > + entry for each entry in the interrupt-names property. Where's interrupt-names? > +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties > + Please refer to the standard PCI bus binding document for a more detailed > + explanation. > +- clocks: Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names: Must include the following entries: > + - free_ck :for reference clock of PCIe subsys > + - sys_ck0 :for clock of Port0 MAC > + - sys_ck1 :for clock of Port1 MAC > + - sys_ck2 :for clock of Port2 MAC > +- resets: Must contain an entry for each entry in reset-names. > + See ../reset/reset.txt for details. > +- reset-names: Must include the following entries: > + - pcie-rst0 :port0 reset > + - pcie-rst1 :port1 reset > + - pcie-rst2 :port2 reset > +- phys: list of PHY specifiers (used by generic PHY framework) > +- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the > + number of PHYs as specified in *phys* property. > +- power-domains: A phandle and power domain specifier pair to the power domain > + which is responsible for collapsing and restoring power to the peripheral > +- bus-range: Range of bus numbers associated with this controller > +- ranges: Describes the translation of addresses for root ports and standard > + PCI regions. The entries must be 6 cells each, where the first three cells > + correspond to the address as described for the #address-cells property > + above, the fourth cell is the physical CPU address to translate to and the > + fifth and six cells are as described for the #size-cells property above. Don't need to define what ranges is here, just what the entries should be: > + - The first three entries are expected to translate the addresses for the root > + port registers, which are referenced by the assigned-addresses property of > + the root port nodes (see below). > + - The remaining entries setup the mapping for the standard I/O and memory > + regions. > + Please refer to the standard PCI bus binding document for a more detailed > + explanation. > + > +In addition, the device tree node must have sub-nodes describing each > +PCIe port interface, having the following mandatory properties: > + > +Required properties: > +- device_type: Must be "pci" > +- assigned-addresses: Address and size of the port configuration registers > +- reg: Only the first four bytes are used to refer to the correct bus number > + and device number. > +- #address-cells: Must be 3 > +- #size-cells: Must be 2 > +- #interrupt-cells: Size representation for interrupts (must be 1) > +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties > + Please refer to the standard PCI bus binding document for a more detailed > + explanation. > +- ranges: Sub-ranges distributed from the PCIe controller node. An empty > + property is sufficient. > +- num-lanes: Number of lanes to use for this port. > + > +Examples: > + > +SoC dtsi: Don't show the board vs. SoC split in examples. And drop all the status properties. > + > + hifsys: syscon@1a000000 { > + compatible = "mediatek,mt7623-hifsys", "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + pcie: pcie-controller@1a140000 { > + compatible = "mediatek,gen2v1-pcie"; > + device_type = "pci"; > + reg = <0 0x1a140000 0 0x1000>; /* PCIe shared registers */ > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupts = , > + , > + ; > + interrupt-map-mask = <0xf800 0 0 0>; > + interrupt-map = <0x0000 0 0 0 &gic GIC_SPI 193 IRQ_TYPE_NONE>, > + <0x0800 0 0 0 &gic GIC_SPI 194 IRQ_TYPE_NONE>, > + <0x1000 0 0 0 &gic GIC_SPI 195 IRQ_TYPE_NONE>; > + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, > + <&hifsys CLK_HIFSYS_PCIE0>, > + <&hifsys CLK_HIFSYS_PCIE1>, > + <&hifsys CLK_HIFSYS_PCIE2>; > + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; > + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, > + <&hifsys MT2701_HIFSYS_PCIE1_RST>, > + <&hifsys MT2701_HIFSYS_PCIE2_RST>; > + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; > + phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>; > + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0 0x1a142000 0 0x1a142000 0 0x1000 /* Port0 registers */ > + 0x82000000 0 0x1a143000 0 0x1a143000 0 0x1000 /* Port1 registers */ > + 0x82000000 0 0x1a144000 0 0x1a144000 0 0x1000 /* Port2 registers */ > + 0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ > + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ > + status = "disabled"; > + > + pcie@1,0 { > + device_type = "pci"; > + assigned-addresses = <0x82000000 0 0x1a142000 0 0x1000>; > + reg = <0x0000 0 0 0 0>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic GIC_SPI 193 IRQ_TYPE_NONE>; > + ranges; > + num-lanes = <1>; > + status = "disabled"; > + }; > + > + pcie@2,0 { > + device_type = "pci"; > + assigned-addresses = <0x82000800 0 0x1a143000 0 0x1000>; > + reg = <0x0800 0 0 0 0>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic GIC_SPI 194 IRQ_TYPE_NONE>; > + ranges; > + num-lanes = <1>; > + status = "disabled"; > + }; > + > + pcie@3,0 { > + device_type = "pci"; > + assigned-addresses = <0x82001000 0 0x1a144000 0 0x1000>; > + reg = <0x1000 0 0 0 0>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic GIC_SPI 195 IRQ_TYPE_NONE>; > + ranges; > + num-lanes = <1>; > + status = "disabled"; > + }; > + }; > + > +Board dts: > + > + &pcie { > + status = "okay"; > + > + pcie@1,0 { > + status = "okay"; > + }; > + }; > -- > 1.9.1 >