Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S969755AbdD3Gsz (ORCPT ); Sun, 30 Apr 2017 02:48:55 -0400 Received: from host.buserror.net ([209.198.135.123]:47977 "EHLO host.buserror.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S969732AbdD3Gsp (ORCPT ); Sun, 30 Apr 2017 02:48:45 -0400 Date: Sun, 30 Apr 2017 01:48:26 -0500 From: Scott Wood To: Christophe Leroy Cc: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Message-ID: <20170430064826.fags33gcyvpqigah@home.buserror.net> References: <20170309094204.ACF5567992@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170309094204.ACF5567992@localhost.localdomain> User-Agent: NeoMutt/20170113 (1.7.2) X-SA-Exim-Connect-IP: 50.171.225.118 X-SA-Exim-Rcpt-To: christophe.leroy@c-s.fr, benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: oss@buserror.net X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -15 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] * -1.5 GREYLIST_ISWHITE The incoming server has been whitelisted for this * recipient and sender Subject: Re: powerpc/8xx: Adding support of IRQ in MPC8xx GPIO X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:57:07 +0000) X-SA-Exim-Scanned: Yes (on host.buserror.net) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1523 Lines: 48 On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote: > This patch allows the use of IRQ to notify the change of GPIO status > on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs > in the Device Tree. > > Ex: > CPM1_PIO_C: gpio-controller@960 { > #gpio-cells = <2>; > compatible = "fsl,cpm1-pario-bank-c"; > reg = <0x960 0x10>; > interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>; > interrupts-mask = <0x0fff>; > interrupt-parent = <&CPM_PIC>; > gpio-controller; > }; > > The property 'interrupts-mask' defines which of the 16 GPIOs have > the associated interrupts defined in the 'interrupts' property. Binding? Should also be named something like "fsl,cpm1-gpio-irq-mask", > static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) > { > struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); > @@ -618,6 +633,7 @@ int cpm1_gpiochip_add16(struct device_node *np) > struct cpm1_gpio16_chip *cpm1_gc; > struct of_mm_gpio_chip *mm_gc; > struct gpio_chip *gc; > + u16 mask; > > cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); > if (!cpm1_gc) > @@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np) > > spin_lock_init(&cpm1_gc->lock); > > + if (!of_property_read_u16(np, "interrupts-mask", &mask)) { > + int i, j; > + > + for (i = 0, j = 0; i < 16; i++) > + if (mask & (1 << (15 - i))) > + cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++); > + } Do we really need to use MSB-first bit numbering here? -Scott