Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751308AbdFAFj5 (ORCPT ); Thu, 1 Jun 2017 01:39:57 -0400 Received: from mail-eopbgr30077.outbound.protection.outlook.com ([40.107.3.77]:24310 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750926AbdFAFjz (ORCPT ); Thu, 1 Jun 2017 01:39:55 -0400 From: Andy Duan To: Florian Fainelli , Rob Herring , Quentin Schulz CC: "mark.rutland@arm.com" , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "thomas.petazzoni@free-electrons.com" Subject: RE: [PATCH v2] net: fec: add post PHY reset delay DT property Thread-Topic: [PATCH v2] net: fec: add post PHY reset delay DT property Thread-Index: AQHS06nRehnVGUCOUUqM6VDa7fPzvKIOsvQAgACRsmCAAAeYgIAAPnTg Date: Thu, 1 Jun 2017 05:39:53 +0000 Message-ID: References: <20170523094808.11102-1-quentin.schulz@free-electrons.com> <20170531164416.ka3hk6a2lybrlngd@rob-hp-laptop> <621b21da-e152-dead-de0f-af17e7c55a38@gmail.com> In-Reply-To: <621b21da-e152-dead-de0f-af17e7c55a38@gmail.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [192.158.241.86] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM4PR0401MB2259;7:CrEYcMf4VNDeaqtkNKU1hZvuxZj0nkRxEr0pv/29JjsFwWeLycAW7Xz67BlgJY495pe0Z4b/76vlRx32g0qdNx5uER1cnNpQe+Bf1fOYkwPdToIM/UucD4GV9c6VM+0L3EE7mBdbeGo2zRHMG9PTu+Ne4PU7yTt2F2nQGepGzivOpJa1wa31JZsIZu/asi57d7nZEmh2PFGGVaHiWEuibERC4Rn81wLkilgxjikJJGXYIFUrJw35TKktXQln+UPzNlQ4EVQpy1dHPvxh1rKLjB29ZDesry4hlGlT8OnbT2w6W/d2AmwhRURcwwqsyvkZcEPDSwnKUMgWJuRJyOTwXA== x-ms-traffictypediagnostic: AM4PR0401MB2259: x-ms-office365-filtering-correlation-id: 32f279cb-f008-4017-420d-08d4a8b0a0d9 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081);SRVR:AM4PR0401MB2259; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917)(9452136761055)(185117386973197)(58145275503218); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(100000700082)(100105000095)(100000701082)(100105300095)(100000702082)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(3002001)(100000703082)(100105400095)(10201501046)(93006095)(93001095)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123558100)(20161123560025)(20161123564025)(20161123555025)(20161123562025)(6072148)(100000704082)(100105200095)(100000705081)(100105500095);SRVR:AM4PR0401MB2259;BCL:0;PCL:0;RULEID:(100000800081)(100110000095)(100000801081)(100110300095)(100000802081)(100110100095)(100000803081)(100110400095)(100000804081)(100110200095)(100000805081)(100110500095);SRVR:AM4PR0401MB2259; x-forefront-prvs: 0325F6C77B x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(39840400002)(39450400003)(39860400002)(39400400002)(39850400002)(39410400002)(377454003)(24454002)(9686003)(38730400002)(6246003)(25786009)(478600001)(99286003)(6116002)(66066001)(54906002)(3846002)(6506006)(6436002)(102836003)(7696004)(54356999)(39060400002)(229853002)(50986999)(53936002)(2950100002)(76176999)(2900100001)(86362001)(55016002)(74316002)(14454004)(93886004)(81166006)(3660700001)(2906002)(5250100002)(7736002)(8936002)(8676002)(33656002)(3280700002)(5660300001)(305945005)(189998001)(4326008);DIR:OUT;SFP:1101;SCL:1;SRVR:AM4PR0401MB2259;H:AM4PR0401MB2260.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:ovrnspm;PTR:InfoNoRecords;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Jun 2017 05:39:53.0510 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0401MB2259 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v515e2nv009575 Content-Length: 3169 Lines: 71 From: Florian Fainelli Sent: Thursday, June 01, 2017 9:53 AM >To: Andy Duan ; Rob Herring ; >Quentin Schulz >Cc: mark.rutland@arm.com; netdev@vger.kernel.org; >devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; >thomas.petazzoni@free-electrons.com >Subject: Re: [PATCH v2] net: fec: add post PHY reset delay DT property > >Le 05/31/17 à 18:39, Andy Duan a écrit : >> From: Rob Herring Sent: Thursday, June 01, 2017 >> 12:44 AM >>> On Tue, May 23, 2017 at 11:48:08AM +0200, Quentin Schulz wrote: >>>> Some PHY require to wait for a bit after the reset GPIO has been >>>> toggled. This adds support for the DT property >>>> `phy-reset-post-delay` which gives the delay in milliseconds to wait after >reset. >>>> >>>> If the DT property is not given, no delay is observed. Post reset >>>> delay greater than 1000ms are invalid. >>>> >>>> Signed-off-by: Quentin Schulz >>>> --- >>>> >>>> v2: >>>> - return -EINVAL when phy-reset-post-delay is greater than 1000ms >>>> instead of defaulting to 1ms, >>>> - remove `default to 1ms` when phy-reset-post-delay > 1000Ms from DT >>>> binding doc and commit log, >>>> - move phy-reset-post-delay property reading before >>>> devm_gpio_request_one(), >>>> >>>> Documentation/devicetree/bindings/net/fsl-fec.txt | 4 ++++ >>>> drivers/net/ethernet/freescale/fec_main.c | 16 +++++++++++++++- >>>> 2 files changed, 19 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt >>>> b/Documentation/devicetree/bindings/net/fsl-fec.txt >>>> index a1e3693cca16..6f55bdd52f8a 100644 >>>> --- a/Documentation/devicetree/bindings/net/fsl-fec.txt >>>> +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt >>>> @@ -15,6 +15,10 @@ Optional properties: >>>> - phy-reset-active-high : If present then the reset sequence using the >GPIO >>>> specified in the "phy-reset-gpios" property is reversed (H=reset state, >>>> L=operation state). >>>> +- phy-reset-post-delay : Post reset delay in milliseconds. If >>>> +present then >>> >>> This needs unit suffix minimally. It should also have a vendor prefix >>> or be made generic. >>> >>> But really, this is a property of the phy and should be in the phy >>> node as should phy-reset-gpios, phy-reset-active-high, phy-supply, etc. >>> >> Yes, it is better to make it general. >> Last year, Uwe Kleine-König's patch "Commit da47b4572056 ("phy: add >support for a reset-gpio specification")" did this, but it was reverted by >commit 948350140ef0 (Revert "phy: add support for a reset-gpio >specification"). And in all phy device driver, only at803x.c add the gpio reset in >currently. > >Getting the binding correct does not prevent us from later moving this reset >code into PHYLIB where it's appropriate. In fact; a correct and generic binding >proposed for FEC here could be used as a basis for all other MAC and PHY >drivers. >-- >Florian I agree with your opinion. Just hope to add the general phy reset interface in phylib and special device driver. Andy