Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751632AbdFALN7 (ORCPT ); Thu, 1 Jun 2017 07:13:59 -0400 Received: from imap0.codethink.co.uk ([185.43.218.159]:33019 "EHLO imap0.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751509AbdFALN5 (ORCPT ); Thu, 1 Jun 2017 07:13:57 -0400 Message-ID: <1496315619.2790.8.camel@codethink.co.uk> Subject: Re: [PATCH 4.4 030/103] drm/amdgpu: Make display watermark calculations more accurate From: Ben Hutchings To: Alex Deucher , Mario Kleiner Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, Greg Kroah-Hartman Date: Thu, 01 Jun 2017 12:13:39 +0100 In-Reply-To: <20170523200859.986280848@linuxfoundation.org> References: <20170523200856.903752266@linuxfoundation.org> <20170523200859.986280848@linuxfoundation.org> Organization: Codethink Ltd. Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1414 Lines: 41 On Tue, 2017-05-23 at 22:08 +0200, Greg Kroah-Hartman wrote: > 4.4-stable review patch. If anyone has any objections, please let me know. > > ------------------ > > From: Mario Kleiner > > commit d63c277dc672e0c568481af043359420fa9d4736 upstream. > > Avoid big roundoff errors in scanline/hactive durations for > high pixel clocks, especially for >= 500 Mhz, and thereby > program more accurate display fifo watermarks. [...] > --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > @@ -1237,14 +1237,14 @@ static void dce_v10_0_program_watermarks > { > struct drm_display_mode *mode = &amdgpu_crtc->base.mode; > struct dce10_wm_params wm_low, wm_high; > - u32 pixel_period; > + u32 active_time; > u32 line_time = 0; > u32 latency_watermark_a = 0, latency_watermark_b = 0; > u32 tmp, wm_mask, lb_vblank_lead_lines = 0; > > if (amdgpu_crtc->base.enabled && num_heads && mode) { > - pixel_period = 1000000 / (u32)mode->clock; > - line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); > + active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock; > + line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535); [...] Won't these multiplications overflow if a >4K display is attached to a 32-bit machine? Ben. -- Ben Hutchings Software Developer, Codethink Ltd.