Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752161AbdFAQcd (ORCPT ); Thu, 1 Jun 2017 12:32:33 -0400 Received: from shadbolt.e.decadent.org.uk ([88.96.1.126]:33076 "EHLO shadbolt.e.decadent.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751951AbdFAPoo (ORCPT ); Thu, 1 Jun 2017 11:44:44 -0400 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit MIME-Version: 1.0 From: Ben Hutchings To: linux-kernel@vger.kernel.org, stable@vger.kernel.org CC: akpm@linux-foundation.org, "Leon Romanovsky" , "Matan Barak" , "Saeed Mahameed" , "Eli Cohen" Date: Thu, 01 Jun 2017 16:43:15 +0100 Message-ID: X-Mailer: LinuxStableQueue (scripts by bwh) Subject: [PATCH 3.16 017/212] IB/mlx5: Fix retrieval of index to first hi class bfreg In-Reply-To: X-SA-Exim-Connect-IP: 82.70.136.246 X-SA-Exim-Mail-From: ben@decadent.org.uk X-SA-Exim-Scanned: No (on shadbolt.decadent.org.uk); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2440 Lines: 86 3.16.44-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Eli Cohen commit 0b80c14f009758cefeed0edff4f9141957964211 upstream. First the function retrieving the index of the first hi latency class blue flame register. High latency class bfregs are located right above medium latency class bfregs. Fixes: c1be5232d21d ('IB/mlx5: Fix micro UAR allocator') Signed-off-by: Eli Cohen Reviewed-by: Matan Barak Signed-off-by: Leon Romanovsky Signed-off-by: Saeed Mahameed [bwh: Backported to 3.16: - s/bfreg/uuar/g - Adjust context] Signed-off-by: Ben Hutchings --- drivers/infiniband/hw/mlx5/qp.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -367,12 +367,21 @@ static int next_uuar(int n) return n; } +enum { + /* this is the first blue flame register in the array of bfregs assigned + * to a processes. Since we do not use it for blue flame but rather + * regular 64 bit doorbells, we do not need a lock for maintaiing + * "odd/even" order + */ + NUM_NON_BLUE_FLAME_BFREGS = 1, +}; + static int num_med_uuar(struct mlx5_uuar_info *uuari) { int n; n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - - uuari->num_low_latency_uuars - 1; + uuari->num_low_latency_uuars - NUM_NON_BLUE_FLAME_BFREGS; return n >= 0 ? n : 0; } @@ -385,17 +394,9 @@ static int max_uuari(struct mlx5_uuar_in static int first_hi_uuar(struct mlx5_uuar_info *uuari) { int med; - int i; - int t; med = num_med_uuar(uuari); - for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { - t++; - if (t == med) - return next_uuar(i); - } - - return 0; + return next_uuar(med); } static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) @@ -421,6 +422,8 @@ static int alloc_med_class_uuar(struct m for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { if (uuari->count[i] < uuari->count[minidx]) minidx = i; + if (!uuari->count[minidx]) + break; } uuari->count[minidx]++; @@ -435,6 +438,7 @@ static int alloc_uuar(struct mlx5_uuar_i mutex_lock(&uuari->lock); switch (lat) { case MLX5_IB_LATENCY_CLASS_LOW: + BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); uuarn = 0; uuari->count[uuarn]++; break;