Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751591AbdFBXuw (ORCPT ); Fri, 2 Jun 2017 19:50:52 -0400 Received: from mga11.intel.com ([192.55.52.93]:12689 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751180AbdFBXt7 (ORCPT ); Fri, 2 Jun 2017 19:49:59 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,287,1493708400"; d="scan'208";a="110334809" From: thor.thayer@linux.intel.com To: wsa@the-dreams.de, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, thor.thayer@linux.intel.com Cc: davem@davemloft.net, gregkh@linuxfoundation.org, mchehab@kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCHv3 1/4] ARM: dts: socfpga: Add Altera I2C Controller to CycloneV Date: Fri, 2 Jun 2017 18:52:36 -0500 Message-Id: <1496447559-19782-2-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496447559-19782-1-git-send-email-thor.thayer@linux.intel.com> References: <1496447559-19782-1-git-send-email-thor.thayer@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2486 Lines: 99 From: Thor Thayer Add the Altera I2C Controller to the CycloneV SoCFPGA device tree. Signed-off-by: Thor Thayer --- v2 Remove altr, from fifo-size. Rename compatible string to "altr,softip-i2c" v3 Add version to commpatible string "altr,softip-i2c-v1.0" --- arch/arm/boot/dts/socfpga.dtsi | 13 ++++++++++--- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 28 +++++++++++++++++++++++++++- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b2674bd..d69c13d 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -133,6 +133,13 @@ #address-cells = <1>; #size-cells = <0>; + clk_0: clk_0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_0-clk"; + }; + osc1: osc1 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -529,11 +536,11 @@ }; }; - fpga_bridge0: fpga_bridge@ff400000 { + fpga_bridge0: fpga_bridge@ff200000 { compatible = "altr,socfpga-lwhps2fpga-bridge"; - reg = <0xff400000 0x100000>; + reg = <0xff200000 0x00200000>; resets = <&rst LWHPS2FPGA_RESET>; - clocks = <&l4_main_clk>; + clocks = <&clk_0>; }; fpga_bridge1: fpga_bridge@ff500000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 155829f..f99576b 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -68,6 +68,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + }; &can0 { @@ -101,7 +102,7 @@ }; &i2c0 { - status = "okay"; + status = "disabled"; clock-frequency = <100000>; /* @@ -176,3 +177,28 @@ &usb1 { status = "okay"; }; + +&fpga_bridge0 { + reg-names = "axi_h2f_lw"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x00000001 0x00080000 0xff280000 0x00000040>; + + i2c_0: i2c@0x100080000 { + compatible = "altr,softip-i2c-v1.0"; + reg = <0x00000001 0x00080000 0x00000040>; + interrupt-parent = <&intc>; + interrupts = <0 43 4>; + clocks = <&clk_0>; + fifo-size = <4>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + }; +}; -- 2.7.4