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From: Alan Tull <atull@kernel.org>
Date: Mon, 5 Jun 2017 10:12:14 -0500
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Subject: Re: [PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
To: Joshua Clayton <stillcompiling@gmail.com>
Cc: Moritz Fischer <moritz.fischer@ettus.com>,
        Anatolij Gustschin <agust@denx.de>,
        Bastian Stender <bst@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>,
        Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
        Sascha Hauer <kernel@pengutronix.de>,
        Fabio Estevam <fabio.estevam@nxp.com>,
        Russell King <linux@armlinux.org.uk>, linux-fpga@vger.kernel.org,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>
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On Fri, Jun 2, 2017 at 3:30 PM, Joshua Clayton <stillcompiling@gmail.com> wrote:
> Add support for Altera FPGA connected to an spi port
> to the evi devicetree file
>
> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>

Signed-off-by: Alan Tull <atull@kernel.org>

> ---
>  arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
> index 24fe093a66db..59aebbc95671 100644
> --- a/arch/arm/boot/dts/imx6q-evi.dts
> +++ b/arch/arm/boot/dts/imx6q-evi.dts
> @@ -82,6 +82,15 @@
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
>         status = "okay";
> +
> +       fpga: fpga@0 {
> +               compatible = "altr,fpga-passive-serial";
> +               spi-max-frequency = <20000000>;
> +               reg = <0>;
> +               pinctrl-0 = <&pinctrl_fpgaspi>;
> +               nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> +               nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
> +       };
>  };
>
>  &ecspi3 {
> @@ -313,6 +322,13 @@
>                 >;
>         };
>
> +       pinctrl_fpgaspi: fpgaspigrp {
> +               fsl,pins = <
> +                       MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
> +                       MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
> +               >;
> +       };
> +
>         pinctrl_gpminand: gpminandgrp {
>                 fsl,pins = <
>                         MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> --
> 2.11.0
>