Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751478AbdFETIH (ORCPT ); Mon, 5 Jun 2017 15:08:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:44752 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751348AbdFETHR (ORCPT ); Mon, 5 Jun 2017 15:07:17 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5C8B523A4F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=atull@kernel.org From: Alan Tull To: Greg Kroah-Hartman Cc: linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org, Moritz Fischer , delicious.quinoa@gmail.com, Joshua Clayton , Alan Tull Subject: [PATCH 07/10] ARM: dts: imx6q-evi: support altera-ps-spi Date: Mon, 5 Jun 2017 14:07:38 -0500 Message-Id: <20170605190741.10508-8-atull@kernel.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170605190741.10508-1-atull@kernel.org> References: <20170605190741.10508-1-atull@kernel.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1186 Lines: 47 From: Joshua Clayton Add support for Altera FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton Signed-off-by: Alan Tull --- arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index fd2220aa49e2..55ec775d4435 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -94,6 +94,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; status = "okay"; + + fpga: fpga@0 { + compatible = "altr,fpga-passive-serial"; + spi-max-frequency = <20000000>; + reg = <0>; + pinctrl-0 = <&pinctrl_fpgaspi>; + nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + }; }; &ecspi3 { @@ -319,6 +328,13 @@ >; }; + pinctrl_fpgaspi: fpgaspigrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + pinctrl_gpminand: gpminandgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -- 2.11.0