Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751576AbdFFQdp (ORCPT ); Tue, 6 Jun 2017 12:33:45 -0400 Received: from mail-ot0-f194.google.com ([74.125.82.194]:34625 "EHLO mail-ot0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751200AbdFFQdn (ORCPT ); Tue, 6 Jun 2017 12:33:43 -0400 MIME-Version: 1.0 In-Reply-To: References: From: Fabio Estevam Date: Tue, 6 Jun 2017 13:33:41 -0300 Message-ID: Subject: Re: [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate To: Stefan Agner Cc: Shawn Guo , Sascha Hauer , Stephen Boyd , Dong Aisheng , David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , "robh+dt@kernel.org" , Mark Rutland , han.xu@nxp.com, Fabio Estevam , =?UTF-8?Q?Lothar_Wa=C3=9Fmann?= , "linux-mtd@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , linux-clk@vger.kernel.org, linux-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 544 Lines: 12 On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner wrote: > The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT > and NAND_CLK_ROOT. However, the gate has been in the chain of the > latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT > only, e.g. as required by APBH-Bridge-DMA. > > Add new clocks which represent the clock after the gate, and use a > shared clock gate to correctly model the hardware. > > Signed-off-by: Stefan Agner Tested-by: Fabio Estevam