Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751719AbdFGMh7 (ORCPT ); Wed, 7 Jun 2017 08:37:59 -0400 Received: from mx08-00252a01.pphosted.com ([91.207.212.211]:46085 "EHLO mx08-00252a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751637AbdFGMhz (ORCPT ); Wed, 7 Jun 2017 08:37:55 -0400 Subject: Re: [PATCH 1/2] clk: bcm2835: Add AUX interrupt controller To: Alexander Stein , linux-kernel@vger.kernel.org Cc: Mark Rutland , Rob Herring , Stephen Boyd , Florian Fainelli , Eric Anholt , Stefan Wahren , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-rpi-kernel@lists.infradead.org References: <79d4534c-49fe-3af4-13d8-2aaf22120d43@raspberrypi.org> <3148562.tSrsoIclEp@ws-stein> From: Phil Elwell Message-ID: <369bb235-77fb-60ad-61d8-3de039e0f838@raspberrypi.org> Date: Wed, 7 Jun 2017 13:37:41 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <3148562.tSrsoIclEp@ws-stein> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-07_08:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_notspam policy=outbound_spam score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706070233 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2779 Lines: 69 On 07/06/2017 13:07, Alexander Stein wrote: > On Wednesday 07 June 2017 12:11:45, Phil Elwell wrote: >> Devices in the AUX block share a common interrupt line, with a register >> indicating which devices have active IRQs. Expose this as a nested >> interrupt controller to avoid IRQ sharing problems (easily observed if >> UART1 and SPI1/2 are enabled simultaneously). >> >> Signed-off-by: Phil Elwell >> --- >> drivers/clk/bcm/clk-bcm2835-aux.c | 120 >> ++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) >> >> diff --git a/drivers/clk/bcm/clk-bcm2835-aux.c >> b/drivers/clk/bcm/clk-bcm2835-aux.c index bd750cf..41e0702 100644 >> --- a/drivers/clk/bcm/clk-bcm2835-aux.c >> +++ b/drivers/clk/bcm/clk-bcm2835-aux.c >> [...] >> +struct auxirq_state { >> + void __iomem *status; >> + u32 enables; >> + struct irq_domain *domain; >> + struct regmap *local_regmap; >> +}; >> + >> +static struct auxirq_state auxirq __read_mostly; >> + >> +static irqreturn_t bcm2835_auxirq_handler(int irq, void *dev_id) >> +{ >> + u32 stat = readl_relaxed(auxirq.status); >> + u32 masked = stat & auxirq.enables; > > Doesn't this hide any spurious interrupts? Is this acceptable? I mean getting > informed about spurious interrupts seems nice to me, as it indicates a > hardware/configuration problem. Thanks for the reply. This interrupt handler is capable of dispatching multiple interrupts but must return a single value - IRQ_HANDLED or IRQ_NONE. I've assumed that returning IRQ_NONE repeatedly will trigger the spurious interrupt detection. This implementation returns IRQ_HANDLED if any unmasked interrupts are raised, otherwise it returns IRQ_NONE. Therefore provided any spurious interrupt isn't always coincident with a real interrupt then it ought eventually to be identified as spurious. The alternative - returning IRQ_NONE if there are any spurious interrupts - seems prone to causing collateral damage. What did you have in mind? >> + if (masked & BCM2835_AUXIRQ_UART_MASK) >> + generic_handle_irq(irq_linear_revmap(auxirq.domain, >> + BCM2835_AUXIRQ_UART_IRQ)); >> + >> + if (masked & BCM2835_AUXIRQ_SPI1_MASK) >> + generic_handle_irq(irq_linear_revmap(auxirq.domain, >> + BCM2835_AUXIRQ_SPI1_IRQ)); >> + >> + if (masked & BCM2835_AUXIRQ_SPI2_MASK) >> + generic_handle_irq(irq_linear_revmap(auxirq.domain, >> + BCM2835_AUXIRQ_SPI2_IRQ)); >> + >> + return (masked & BCM2835_AUXIRQ_ALL_MASK) ? IRQ_HANDLED : IRQ_NONE; >> +} > > How does interrupt acknowledgement work in these 3 interrupts work? The interrupt "controller" is just combinatorial logic on the three level-sensitive interrupt lines from the devices. Interrupts must be acknowledged and cleared at source. Phil