Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752198AbdFGTiX (ORCPT ); Wed, 7 Jun 2017 15:38:23 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:36715 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751704AbdFGTiV (ORCPT ); Wed, 7 Jun 2017 15:38:21 -0400 Subject: Re: [PATCH net-next 3/5] net: dsa: add CPU and DSA ports as VLAN members To: Vivien Didelot , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, kernel@savoirfairelinux.com, "David S. Miller" , Andrew Lunn References: <20170606205631.22880-1-vivien.didelot@savoirfairelinux.com> <20170606205631.22880-4-vivien.didelot@savoirfairelinux.com> From: Florian Fainelli Message-ID: <2e49ee11-3ced-3838-c939-4eb847d3fb1e@gmail.com> Date: Wed, 7 Jun 2017 12:38:16 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <20170606205631.22880-4-vivien.didelot@savoirfairelinux.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 774 Lines: 18 On 06/06/2017 01:56 PM, Vivien Didelot wrote: > In a multi-chip switch fabric, it is currently the responsibility of the > driver to add the CPU or DSA (interconnecting chips together) ports as > members of a new VLAN entry. This makes the drivers more complicated. > > We want the DSA drivers to be stupid and the DSA core being the one > responsible for caring about the abstracted switch logic and topology. > > Make the DSA core program the CPU and DSA ports as part of the VLAN. > > This makes all chips of the data path to be aware of VIDs spanning the > the whole fabric and thus, seamlessly add support for cross-chip VLAN. > > Signed-off-by: Vivien Didelot Reviewed-by: Florian Fainelli -- Florian