Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751789AbdFGUmh (ORCPT ); Wed, 7 Jun 2017 16:42:37 -0400 Received: from mga05.intel.com ([192.55.52.43]:30997 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751694AbdFGUmf (ORCPT ); Wed, 7 Jun 2017 16:42:35 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,311,1493708400"; d="scan'208";a="1139019205" Reply-To: thor.thayer@linux.intel.com Subject: Re: [PATCHv3 1/4] ARM: dts: socfpga: Add Altera I2C Controller to CycloneV To: Steffen Trumtrar Cc: wsa@the-dreams.de, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, davem@davemloft.net, gregkh@linuxfoundation.org, mchehab@kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <1496447559-19782-1-git-send-email-thor.thayer@linux.intel.com> <1496447559-19782-2-git-send-email-thor.thayer@linux.intel.com> <73vao9vcsq.fsf@pengutronix.de> From: Thor Thayer Message-ID: Date: Wed, 7 Jun 2017 15:45:50 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <73vao9vcsq.fsf@pengutronix.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2431 Lines: 87 Hi Steffen, On 06/06/2017 01:40 AM, Steffen Trumtrar wrote: > > Hi! > > thor.thayer@linux.intel.com writes: > >> From: Thor Thayer >> >> Add the Altera I2C Controller to the CycloneV SoCFPGA device tree. >> >> Signed-off-by: Thor Thayer >> --- >> v2 Remove altr, from fifo-size. >> Rename compatible string to "altr,softip-i2c" >> v3 Add version to commpatible string "altr,softip-i2c-v1.0" >> --- >> arch/arm/boot/dts/socfpga.dtsi | 13 ++++++++++--- >> arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 28 +++++++++++++++++++++++++++- >> 2 files changed, 37 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi >> index b2674bd..d69c13d 100644 >> --- a/arch/arm/boot/dts/socfpga.dtsi >> +++ b/arch/arm/boot/dts/socfpga.dtsi >> @@ -133,6 +133,13 @@ >> #address-cells = <1>; >> #size-cells = <0>; >> >> + clk_0: clk_0 { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <50000000>; >> + clock-output-names = "clk_0-clk"; >> + }; >> + >> osc1: osc1 { >> #clock-cells = <0>; >> compatible = "fixed-clock"; >> @@ -529,11 +536,11 @@ >> }; >> }; >> >> - fpga_bridge0: fpga_bridge@ff400000 { >> + fpga_bridge0: fpga_bridge@ff200000 { >> compatible = "altr,socfpga-lwhps2fpga-bridge"; >> - reg = <0xff400000 0x100000>; >> + reg = <0xff200000 0x00200000>; >> resets = <&rst LWHPS2FPGA_RESET>; >> - clocks = <&l4_main_clk>; >> + clocks = <&clk_0>; >> }; >> > > Why this change? This looks wrong and unrelated. The LWHPS2FPGA bridge > is at 0xff400000, so it is correct the way it is or not? > Yes, good point. I was using the LWHPS2FPGA slave bus so I shouldn't change this one. I'll add the slave version. Thanks, Thor >> fpga_bridge1: fpga_bridge@ff500000 { >> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts >> index 155829f..f99576b 100644 >> --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts >> +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts >> @@ -68,6 +68,7 @@ >> regulator-min-microvolt = <3300000>; >> regulator-max-microvolt = <3300000>; >> }; >> + >> }; > > ??? > Whoops. I should remove the extra space. Thanks! > > (...) > > > Best regards, > Steffen >