Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752091AbdFHELn (ORCPT ); Thu, 8 Jun 2017 00:11:43 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:54510 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750819AbdFHELj (ORCPT ); Thu, 8 Jun 2017 00:11:39 -0400 From: Chris Packham To: bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Cc: Chris Packham , Rob Herring , Mark Rutland , Russell King , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 3/4] ARM: l2x0: add arm,ecc-enable property for aurora Date: Thu, 8 Jun 2017 16:11:23 +1200 Message-Id: <20170608041124.4624-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170608041124.4624-1-chris.packham@alliedtelesis.co.nz> References: <20170608041124.4624-1-chris.packham@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1944 Lines: 43 The aurora cache on the Marvell Armada-XP SoC supports ECC protection for the L2 data arrays. Add a "arm,ecc-enable" device tree property which can be used to enable this. Signed-off-by: Chris Packham --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++ arch/arm/mm/cache-l2x0.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index d9650c1788f4..6316e673307a 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -76,6 +76,8 @@ Optional properties: specified to indicate that such transforms are precluded. - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310). - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310). +- arm,ecc-enable : enable ECC protection on the L2 cache +- arm,ecc-disable : disable ECC protection on the L2 cache - arm,outer-sync-disable : disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that will randomly hang unless outer sync operations are disabled. diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2cc2653b046f..4f0e6d9b151d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct device_node *np, mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; } + if (of_property_read_bool(np, "arm,ecc-enable")) { + mask |= L2C_AUX_CTRL_EVTMON_ENABLE; + val |= L2C_AUX_CTRL_EVTMON_ENABLE; + } else if (of_property_read_bool(np, "arm,ecc-disable")) { + mask |= L2C_AUX_CTRL_EVTMON_ENABLE; + } + if (of_property_read_bool(np, "arm,parity-enable")) { mask |= L2C_AUX_CTRL_PARITY_ENABLE; val |= L2C_AUX_CTRL_PARITY_ENABLE; -- 2.13.0