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Date: Thu, 8 Jun 2017 16:53:14 -0500
From: Rob Herring <robh@kernel.org>
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>, linux-kernel@vger.kernel.org,
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        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>,
        Kumar Gala <galak@codeaurora.org>, Andrew Lunn <andrew@lunn.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        Gregory Clement <gregory.clement@free-electrons.com>,
        Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
        Yehuda Yitschak <yehuday@marvell.com>,
        Antoine Tenart <antoine.tenart@free-electrons.com>,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding
 for the Marvell GICP
Message-ID: <20170608215314.hv2jkqbgmytjcazt@rob-hp-laptop>
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On Thu, Jun 08, 2017 at 02:10:23PM +0200, Thomas Petazzoni wrote:
> Hello,
> 
> On Wed, 7 Jun 2017 17:24:20 -0500, Rob Herring wrote:
> > On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote:
> > > This commit adds the Device Tree binding documentation for the Marvell
> > > GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
> > > using memory transactions. It is used by the ICU unit in the Marvell
> > > CP110 block to turn wired interrupts inside the CP into SPI interrupts
> > > at the GIC level in the AP.  
> > 
> > Sounds like an MSI block?
> 
> Marc Zyngier answered on this (much better than I could have done).
> 
> > > +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
> > > +  for this GICP  
> > 
> > These are base+size?
> 
> Correct. Does your question suggest that I should update the binding
> document to make this explicit?

Yes, please.

Rob