Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751757AbdFHV4E (ORCPT ); Thu, 8 Jun 2017 17:56:04 -0400 Received: from mail-ot0-f177.google.com ([74.125.82.177]:36765 "EHLO mail-ot0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751475AbdFHV4C (ORCPT ); Thu, 8 Jun 2017 17:56:02 -0400 Date: Thu, 8 Jun 2017 16:56:00 -0500 From: Rob Herring To: Thomas Petazzoni Cc: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Nadav Haklai , Hanna Hawa , Yehuda Yitschak , Antoine Tenart , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: add DT binding for the Marvell ICU Message-ID: <20170608215600.tfvxnx6nlhnmswof@rob-hp-laptop> References: <1496398017-6487-1-git-send-email-thomas.petazzoni@free-electrons.com> <1496398017-6487-3-git-send-email-thomas.petazzoni@free-electrons.com> <20170607223317.hkpak5y2oalktjqe@rob-hp-laptop> <20170608141202.14e4801e@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170608141202.14e4801e@free-electrons.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1109 Lines: 32 On Thu, Jun 08, 2017 at 02:12:02PM +0200, Thomas Petazzoni wrote: > Hello, > > On Wed, 7 Jun 2017 17:33:17 -0500, Rob Herring wrote: > > > > +Example: > > > + > > > +icu: interrupt-controller@1e0000 { > > > + compatible = "marvell,cp110-icu"; > > > + reg = <0x1e0000 0x10>; > > > + #interrupt-cells = <3>; > > > + interrupt-controller; > > > + interrupt-parent = <&gic>; > > > > If you have a parent, then you should have some interrupts. I guess that > > would be your ranges property? I suppose that is fine. > > The ranges of interrupts available is defined by the gicp node. Indeed, > as explained in the cover letter: > > - We have one GICP in the SoC, providing a number of GIC SPI interrupts > > - We have one ICU per CP in the SoC. So for example in the Armada 8K, > we have two CPs, and therefore two ICUs. > > So the range of available GIC SPI interrupts it not associated to each > ICU, it's a global range of GIC SPI interrupts: each can freely be > allocated by any of the ICUs in the system. Okay, I guess I have no issues with this one. Acked-by: Rob Herring